ADC with uDMA channel order mismatch

Hello Christian,

Can you please try the following

MAP_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_ADC0);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);

to make sure that the ADC controller is reset before being used. This will ensure the FIFO pointers due to a previous run does not get misaligned.

Regards
Amit

Hello Amit.

It didn't help. There is still a rotation in the channel order.

What I've seen is, that after the first time start of the program the order is correct (I've set a breakpoint in the ADC0SS0uDMATransferFinishedISR function). After pressing F8 (Resume) only two scatter gather transfers have the correct order and for the remaining 98 transfers the order is wrong. After pressing F8 once again, all transfers have the wrong order.

I't seems really strange to me.

Any other suggestions?

Thank you

BR

Christian

Hello Christian

Have you kept the Register or Memory window open in CCS with the address space of the ADC in the view?

Regards
Amit

Hello Amit.

No I've only the "Expressions" window opened to see the values of the Voltages-variable.

I've again read the data sheet of µDMA. It says that the ADC module generates a µDMA burst request when the FIFO is half full. And the arbitration size should be set to the same as the number of data items the peripheral can accommodate when making a burst request.

This means that the burst request for ADC0 SS0 occures when it has sampled four channels. But I have configured six channels and I cannot set arbitration size to six.
Can this be a problem?

BR
Christian

Hello Christian,

In this case the value would be 4. The FIFO shall always generate a DMA Burst Request on half full.

Regards
Amit

Hello Amit,

ok, but when a burst request is generated after FIFO half full (4 values), six values will be transfered because a burst request cannot be canceled, isn't it?

BR
Christian

Hello Christian

The Transfer size must be 6 and Arb Size as 4. So when the Burst Request is generated 4 values will be read out in Burst and the Last 2 using single requests.

Regards
Amit

Hello Amit.

With this settings rotation didn't happen. But for testing I've attached CH0 and CH5 to 3.3V and now I can see that CH0 Shows 4095 but CH5 shows 0. So something still isn't working with this.

I've also tried to fetch the ADC data without µDMA but with ADCSequenceDataGet function called in ISR. There is also a channel Rotation happening.

BR
Christian

Hello Christian,

Can you please share the CCS project so that I can test it?

Regards
Amit

Hello Amit.

here it is. It's running on the Tiva-C  launchpad.

Thank you for your time.

BR

Christian

2235.ADC_uDMA.zip

Hello Christian

I ran the test code and it is working as expected

1. There is no SysCtlClockSet function call, which will cause the CPU to run with 16MHz PIOSC clock and slowing down the CPU. I would suggest using the function to bring the system clock upto 80MHz
2. The Interrupt Handler is doing way more tasks then what is meant to. If you could do slim down the interrupt handler for just re-init and move the processing tasks into the main, it will make the DMA reinit faster.

Regards
Amit

Hi Amit.

Not on my Launchpad.
Set the SystemClock to 80Mhz. => no change.

Now I've found a working solution for me too:
Configure the ADC SS0 to generate an interrupt after each 2nd channel and µDMA arbitration after two transfers. This does the job.

Thanks for your help.
BR
Christian