Hello !
There is a problem with DMA channel mixed with QSSI slave receive mode.
System is based on TIVA TM4C129NCPDT. TIVA runs on 120MHz and receives data frames from external source via QSSI. QSSI frame rate 8kHz, clock rate 8MHz, each frame consist of 28 bytes (224 bits). Data, frame and clock signals are from external master, TIVA works as slave.
TIVA uDMA channel attached to QSSI and configured as ping-pong. Each ping-pong buffer is 420-bytes (15 frames).
Problem is in DMA interrupt request frequency.
DMA interrupt is generating when single (in single mode) or burst (in burst mode) DMA transaction stops, but not each ping-pong changing. So DMA mode looks like usual QSSI interrupt mode.
Here is a part of init code:
void QSSIInit()
{
u8 rSCR = 0;
volatile HwRegsDMA *d = &DMA;
volatile HwRegsSSI *p = &SSI[nSSI_a];
// QSSI
PeripheralOn(concatAB(PERIPH_SSI, nSSI_a));
while(p->CR[1]&QSSI_CR1_SSE);
p->CR[1] = QSSI_CR1_SSE_SLAVE_OUTPUT_DISABLE;
p->CC = 0;
p->CPSR = SETCPSDVCR;
rSCR = SETSCR;
p->CR[0] = (((u32)rSCR)<<8) | QSSI_CR0_SPH_CAPTURE_SECOND_CLOCK | QSSI_CR0_SPO_HIGH_DATA_NOTRANSFER | QSSI_CR0_DSS_16_BIT;
// uDMA
d->CFG = 1;
d->PRIO.SET |= 1<<DMA_A_CHANNEL;
d->ALT.CLR |= 1<<DMA_A_CHANNEL;
d->USEBURST.CLR |= 1<<DMA_A_CHANNEL;
d->REQMASK.CLR |= 1<<DMA_A_CHANNEL;
paramDMA[0][DMA_A_CHANNEL].SRCENDP = (u32)&p->DR;
paramDMA[1][DMA_A_CHANNEL].SRCENDP = (u32)&p->DR;
paramDMA[0][DMA_A_CHANNEL].DSTENDP = ((u32)&SourceDataA) + sizeof(SourceDataA) - 1;
paramDMA[1][DMA_A_CHANNEL].DSTENDP = ((u32)&AlternateSourceDataA) + sizeof(AlternateSourceDataA) - 1;
eControlWordDMA.XFERMODE = 3; // ping-pong
eControlWordDMA.NXTUSEBURST = 0;
eControlWordDMA.XFERSIZE = BUF_RECEIVE_A_BYTE;
eControlWordDMA.ARBSIZE = 2;
eControlWordDMA.SRCPROT0 = 0;
eControlWordDMA.DSTPROT0 = 0;
eControlWordDMA.SRCSIZE = 1;
eControlWordDMA.SRCINC = 3;
eControlWordDMA.DSTSIZE = 1;
eControlWordDMA.DSTINC = 1;
paramDMA[0][DMA_A_CHANNEL].CTL = *((u32*)&eControlWordDMA);
paramDMA[1][DMA_A_CHANNEL].CTL = *((u32*)&eControlWordDMA);
d->CHMAP[1] |= 1<<8;
DMA.ENA.SET |= (1<<DMA_A_CHANNEL);
p->DMACTL = 1;
p->IM |= 1<<4;
p->CR[1] |= QSSI_CR1_SSE_SYNCHRONOUS_SERIAL_ENABLE;
while(p->SR&(1<<2)) *pSourceDataA++ = p->DR;
IntClrEna(NVIC_SSI1);
}
