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HalCoGen MIBSPI1 configuration always generate all pins as functional

Other Parts Discussed in Thread: HALCOGEN

Hello,

I'm using HalCoGEn 4.05.00 for RM48L952ZWT and i need to set SIMO[1]  to GIO mode.

But in generated code is allways

/* SPI1 set all pins to functional */
spiREG1->PC0 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)1U << 3U) /* SCS[3] */
| (uint32)((uint32)1U << 4U) /* SCS[4] */
| (uint32)((uint32)1U << 5U) /* SCS[5] */
| (uint32)((uint32)1U << 8U) /* ENA */
| (uint32)((uint32)1U << 9U) /* CLK */
| (uint32)((uint32)1U << 10U) /* SIMO[0] */
| (uint32)((uint32)1U << 11U) /* SOMI[0] */
| (uint32)((uint32)1U << 17U) /* SIMO[1] */
| (uint32)((uint32)1U << 25U); /* SOMI[1] */

Luděk Hezina

  • I was not able to reproduce your results using HALCoGen 4.05.02. Would you please upgrade and check again?


    /* MIBSPI1 set all pins to functional */ mibspiREG1->PC0 = (uint32)((uint32)1U << 0U) /* SCS[0] */ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ | (uint32)((uint32)1U << 11U) /* SOMI[0] */ | (uint32)((uint32)0U << 17U) /* SIMO[1] */ | (uint32)((uint32)1U << 25U); /* SOMI[1] */

  • Hi,

    I was looking at mibspi setting tab but in Drive enable I have selected Enable SPI1 driver and not mibspi. So my settings for SPI1 is always same.
  • Thank you for explaining. This may help someone else who runs into the same problem.