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Is My Launch Pad Broken?

Other Parts Discussed in Thread: TM4C1294NCPDT

Regulator on my Launch Pad is getting very hot when I connect the VDD Jumper(the one which connects debugger to the micro-controller). I measured current through the jumper about 500mA. This is causing the regulator shut down and no longer powering the micro-controller.

Earlier I was running a code Which had GPIO interrupts on PORTD,PORTC and PORTF. The code ran fine few hours ago  now the board is not powering up. 

  • If that GPIO usage w/in Port C infringed upon (any) PC0-PC3 - you've likely suffered contention between the (main) & (ICDI) MCUs.

    You should remove any/all "external" connections/attachments to your board & insure that correct USB Ports & Power Switch position are maintained.
  • No I haven't touched PC0 - PC3. I am using PC5 and PC6.
  • Hi --.
    You may be aware GPIO ports TM4C launch pads are not +5v tolerant, levels above +3v4 (could) short out the input gates. Have past shorted a +5 volt tolerant GPIO ports (entire MCU) accidently removing common ground wire from GPIO drive circuit located on a vector board.

    Sounds like your launch pad is toasted :(
  • Yes I'm aware of that. I have not applied 5V or above on any GPIO pin.
    One more thing to note is I was using PD7 as input. Can that cause any problem ?
  • PD7 is among the (blessed) "locked pins" - which default as NMI.

    There is a "board recovery routine" w/in LM Flash Programmer - which just might save your board. Surely worth your time/effort to use the "search box" (atop forum) - and attempt recovery...

  • The main is problem I can't supply power to the main Micro-controller as the Micro-controller is drawing about 500mA with nothing connected to it. As result of huge current the on board regulator is shutting down and heating up.
  • Feel your pain - note that when my firm designs boards we employ 0Ω resistors between the 3V3 Reg. and power paths. By opening (or not placing) those smt resistors - we can selectively power (portions) of our board.

    In your case - should you decide to further test/troubleshoot - you'd have to (similarly) divide & conquer the power overload - to determine the overload's source. While ugly - after deep review of board's schematic - you may be able to "selectively slice" the major 3V3 power paths - and in that manner identify "where" the excess current consumption originates.

    Perhaps of greater import - how did this happen? And how can you prevent? It is firm's/my experience that these boards are fairly robust - and such "unwarranted" failures are few, far between... (ESD always lurks - especially during winter/low humidity)

  • Hello cb1-,
    Thank you for your reply.Can you give me some probable cause why this happened?

  • That's more than a bit tricky w/out your isolation of "power paths" - so that the (likely) failed component can be identified. MCU remains high on the suspect list - yet these are amazingly robust - almost never fail w/out (our) help!

    Had you ever connected this board to external components or other boards?
    Had you ever operated via power introduction other than the normal/customary means?
    Was the board handled w/out proper ESD protections? (i.e. grounded wrist-strap and handling only via board edges)

    We note that your reported 500mA current draw appears to be the maximum allowed via a standard USB port. If that's the case - your board is likely drawing in excess of that (high) amount.

    Lastly - despite on-going protest by this reporter & others - LPad (deliberately) provides MCU pin to pin connections - burdening 4 MCU pins. Your board schematic notes this. (visible if you search hard - and squint) Should those pins be set as outputs - and opposite in logic levels - contention results which often (in time) proves destructive. Iirc Port B is one so afflicted - and I don't see Port B mentioned w/in your report...
  • You mentioned disconnecting VDD to Debug the 500ma draw.... yet JP2 disconnect the TM4C1294NCPDT VDD +3v3, JP2 removed for measuring current.  

    From the schematic the TM4C123G ICDI appears direct connected to the +3v3 regulator output via JP3.

    So we can assume you do measure +3v3 at the regulator with JP2 removed. If so the ICDI is likely ok. This is not OTG port providing +5v to the +3v3 regulator? As you can also power the LP via OTG +5v thus PD6 can be used for a fault input PQ4 (LP is not configured USB fault) rather is the EN2 pin on switch U4 when OTG is used in host mode versus device mode, it controls (Target_Vbus/3.2c). The selection of either USB +5 power source Is handled via JP1, defaults 3-4 no other jumpers should be installed on JP1.