bug in ADCClockConfigGet()

Other Parts Discussed in Thread: TM4C129EKCPDT

I am using version version 2.1.1.71 of the TivaWare library (IAR version) on a TM4C129EKCPDT chip.

There appears to be a bug in the ADCClockConfigGet() function. I set breakpoints in the following code and examined some register contents:

void Adc::initialize(void)

{

    U32 divider = 0;

     // the following call should return a setting of 0x00000071, which is the

    // default after a reset

    U32 clkSetting = ADCClockConfigGet((U32)ADC0, &divider);

    //!!! It returns 0x00000070 instead.

    // explicitly set the clock to the reset default value

    ADCClockConfigSet((U32)ADC0, 0x00000071, 1);

    clkSetting = ADCClockConfigGet((U32)ADC0, &divider);

    //!!! It still returns 0x00000070.

}

After the first call to ADCClockConfigGet(), it returns a value of 0x00000070, with a divisor value of 1. This corresponds to ADC_CLOCK_RATE_FULL (0x00000070) + ADC_CLOCK_SRC_PLL (0x00000000). However, the ADC0CC register as viewed from the debugger shows that the clock source is actually ADC_CLOCK_SRC_ALTCLK (0x00000001). The register values match what the data sheet says is the default value on reset.

The call to ADCClockConfigSet() should explicitly set the clock to the default reset value (0x00000071). But a subsequent call to ADCClockConfigGet() has it still returning 0x00000070.

I looked at the library source code for the Get function and it looks like the value of the ADC0CC register’s CS field is not getting ORed into the return value:

uint32_t

ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv)

{

    uint32_t ui32Config;

    //

    // Check the argument.

    //

    ASSERT(ui32Base == ADC0_BASE);

    //

    // Read the current configuration.

    //

    ui32Config = HWREG(ui32Base + ADC_O_CC);

    //

    // If the clock divider was requested provide the current value.

    //

    if(pui32ClockDiv)

    {

        *pui32ClockDiv =

                    ((ui32Config & ADC_CC_CLKDIV_M) >> ADC_CC_CLKDIV_S) + 1;

    }

    //

    // Clear out the divider bits.

    //

    ui32Config &= ~ADC_CC_CLKDIV_M;

    //

    // Add in the sample interval to the configuration.

    //

    ui32Config = (HWREG(ui32Base + ADC_O_PC) & ADC_PC_SR_M) << 4;

    return(ui32Config);

}

Regards,

Dave