• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 29 subscribers
  • Views 2242 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Does TMS570LS20216 have instruction / data cache? What are wait-states for ram / flash?

Steve Meirowsky
Prodigy 70 points
Other Parts Discussed in Thread: TMS570LS20216

Concerning the TMS570LS20216, please answer the following questions:
- ATCM Configuration.  I think the flash is connected to this, but not sure.
- BTCM Configuration.  According to TRM, the silicon is configured for two-banked BTCM, with half the the RAM on each bank, correct?
- Instruction Cache.  I can't tell if the silicon has no cache or it does have cache but not documented.
- Data Cache.  I can't tell if the silicon has no cache or it does have cache but not documented.
- What is the wait-state for the RAM and FLASH?  Please describe for each.
- Are there any additional wait-states for ECC?  Please describe.

 

 

  • 0
    TI__Intellectual 1030 points

    Concerning the TMS570LS20216, please answer the following questions:
    - ATCM Configuration.  I think the flash is connected to this, but not sure.
    Yes, flash is connected to the ATCM interface of the CPU.

    - BTCM Configuration.  According to TRM, the silicon is configured for two-banked BTCM, with half the the RAM on each bank, correct?
    Yes, half the 160k RAM interfaces to the B0TCM interface, and the other half to B1TCM. It's interleaved with the even address RAM interfacing to B0TCM and odd address RAM to B1TCM.

    - Instruction Cache.  I can't tell if the silicon has no cache or it does have cache but not documented.
    No instruction cache.

    - Data Cache.  I can't tell if the silicon has no cache or it does have cache but not documented.
    No data cache.

    - What is the wait-state for the RAM and FLASH?  Please describe for each.
    The wait states required to access RAM and flash at a given system clock frequency (HCLK) are charted in figure 7-3 on page 69 of the SPNS141A datasheet.

    - Are there any additional wait-states for ECC?  Please describe.
    No additional wait states are required for reading from memories with ECC protection.