Hi, I'm having an issue with setting the sysclk speed on the tm4c129 on the Launchpad to its full 120 MHz rate.
I have experience with the NXP LPC1700 and 4300 series and with the STM32F4, but Tiva is new to me. I've read the relevant section of the datasheet and think I'm interpreting it correctly, but as soon as I switch the system clock over to the PLL output, the processor becomes unresponsive.
I know that there's probably a library routine to do this, but I'm a hobbyist and enjoy programming microcontrollers at the bare metal register level.
Here's my code; can someone tell me where I'm going wrong? Thanks. BTW, the board has a 25 MHz crystal connected to MOSC.
#define MINT 64
#define MFRAC 0
#define N 4
#define Q 0
#define PDIV 3
#define FBCHT 0x6
#define EBCHT 0x6
#define FBCE 0
#define EBCE 0
#define FWS 0x5
#define EWS 0x5
/*
* HardwareInit()
*
* Initializes the processor's clocks and PLL and returns the value of the reset status.
*
*/
uint32_t
HardwareInit(void)
{
uint32_t reset_cause;
reset_cause = SYSCTL->RESC; // read clock control and status register to get cause of reset bits
SYSCTL->RESC = 0; // clear reset flags
/*
* Perform oscillator/PLL setup for 120 MHz SYSCLK speed
*/
SYSCTL->MOSCCTL |= 1 << 4; // high speed crystal connected to MOSC (>= 10 MHz)
SYSCTL->MOSCCTL &= ~(1 << 2); // enable external oscillator
SYSCTL->MOSCCTL &= ~(1 << 3); // power up the main oscillator
while(!(SYSCTL->RIS & (1 << 8)))
; // wait for oscillator ready
SYSCTL->RSCLKCFG &= ~(0b11111111 << 20); // clear oscillator and PLL source field
SYSCTL->RSCLKCFG |= (0x3 << 20); // set MOSC as oscillator source
SYSCTL->RSCLKCFG |= (0x3 << 24); // set MOSC as PLL input source
SYSCTL->PLLFREQ0 = (MFRAC << 10) | MINT; // set PLL M integer and fractional values
SYSCTL->PLLFREQ1 = (Q << 8) | N; // set PLL N and Q
SYSCTL->PLLFREQ0 |= 1 << 23; // power up the PLL
SYSCTL->MEMTIM0 = (EBCHT << 22) | (EBCE << 21) | (EWS << 16) | (FBCHT << 6) | (FBCE << 5) | FWS; // set memory timing parameters
while(!(SYSCTL->PLLSTAT & 1))
; // wait for PLL to lock
SYSCTL->RSCLKCFG |= (1 << 31) | (1 << 30) | (1 << 28) | PDIV; // set PLL system clock divisor, lock the system clock to the PLL, and force a memory timing register update
/*
* Enable user fault, bus fault, and mm faults
*/
setshcsr(0x70000);
return(reset_cause);
}
