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HalCodeGen: Initializing RM48L952ZWT

Other Parts Discussed in Thread: RM48L952, HALCOGEN

The electrical engineer on this project gave me a document stating a few things that must be done to initialize the CPU in the boot loader. I  am using the TI HalCodeGen utility to generate the C files that I will put into Code Composer Studio (CSS).

I am new to HalCodeGen, so still learning my way around.

Initialize the Power Management Module to enable Core Block #3 and #5, and disable Core Blocks #2, and #4. Write 0x0A050A05 to the LOGICPDPWRCTRL0 register at 0xFFFF0000. Initialize the Power Mangement Module to enable RAM Memory Blocks #1,#2, and #3. Write 0x09090900 to the MEMPDPWRCTRL0 register at 0xFFFF0010.

Configure the Clock Domain Disable Register (CDDIS at 0xFFFFFF3C) to turn off clock domains VCLK2, VCLKA1, VCLKA3, and VCLKA4 by writing 0x00000C38 to CDDIS.

I did not see anything labeled PMM for the first one. I see clock tree and clock source, but neither looks good for the second.

How would I set these initialization tasks using the HalCodeGen?

  • First, do not disable core block #2. See erratum DEVICE#B053. (Not sure which version of silicon you have, but it applies to all versions. Rev D errata list) Core domain #4 is disabled by hardware on the RM48L952. RAM memory blocks 0, 1 and 2 are enabled by default. There is no RAM block 3. (Maybe they meant the third block.) There is no need to change the power management registers for your use case. If it were necessary to change these registers, you would hand modify the code generated by HALCoGen. Take care that all of your changes are within the comments like:

    /* USER CODE BEGIN (9) */
    /* USER CODE END */
    

    This prevents HALCoGen from overwriting your modification in case you need to regenerate the HALCoGen code.