TM4C GPIO interrupt

Hello tMatsu,

From the datasheet to which you linked:

3.1.2.1 Level-Sensitive and Pulse Interrupts

The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts.

A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.

When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and Software Control of Interrupts” on page 126 for more information). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing.

So, in summary, the level must be at the appropriate level for a minimum of 1 clock cycle. Once asserted, the interrupt will re-assert after execution of the ISR as long as the level remains in the defined assert state (high or low). If you are having issues with chatter, is this really the configuration you want?  i.e., maybe, if you are looking for a single interrupt when the signal goes high or low, then you really need an edge triggered interrupt instead?