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flag register about instruction movs

junwon kim
Intellectual 350 points
Other Parts Discussed in Thread: TM4C123GH6PGE

In CCSv5, with TM4C123GH6PGE,

when executing instruction ' movs r0, #0x80000000'

carry bit and negative bit is set.

Why these bits are set?

  • 0
    TI__Guru* 84285 points
    This is a question about the ARM architecture. This question is answered by the ARM technical reference manual. Questions about the manual should be directed to an ARM forum.
  • 0 in reply to Archaeologist
    Guru 47900 points

    Bravo "Archaeologist." Questions should have (bit) more TM4C specific relevance.    (I'll thus "defer" my question re: Pyramid alignment... my Archaeological Reference Manual (ARM) being currently unavailable)

    We note that the MSb usually indicates "negative" when set - and that the TRM defines/describes all others...

  • 0 in reply to cb1
    Intellectual 350 points
    Thanks for replying.
    How does that instruction make carry bit set?
    Does it have any relation with carry bit? by just moving immediate value to register?
  • 0 in reply to junwon kim
    Guru 26105 points

    Hi,

    More inside details (maybe a little bit outdated, but as principle should be the same) may be found in this link.

  • 0 in reply to Petrei
    Intellectual 350 points
    Thanks for replying, but I cannot find about contents of carry bit when executing that mov instruction.
    Is it right that carry bit set when executing "movs r0, #0x80000000"?
  • 0 in reply to junwon kim
    Guru 11940 points

    Setting flags from a 'mov' instruction is an optional feature of the ARM/Thumb instruction set. The added suffix 's' specifies exactly that.

    Look here: infocenter.arm.com/.../index.jsp

  • 0 in reply to f. m.
    Intellectual 350 points
    Thanks for replying.
    I know about 's'option and carry bit.
    My question is 'why carry bit is set by that instruction?'
    It seems that 'movs' instruction doesn't related with carry bit set condition.
  • 0 in reply to junwon kim
    Guru 26105 points

    Condition flags

    If S is specified, the instruction:

    • Updates the N and Z flags according to the result.
    • Can update the C flag during the calculation of Operand2.
    • Does not affect the V flag.

    • Operand2: In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions.
      When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other constant.