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Programming of internal flash while executing

Mathieu Patte
Intellectual 440 points
Other Parts Discussed in Thread: TMS570LS3137

Hello,

I am looking into update the internal flash memory contents while keeping my application running on a TMS570LS3137. 

I intend to run from flash memory bank1 while update the contents bank0. 

However exception vectors are located near address 0x0. I can remap IRQ using hardware vectoring of the VIM, but I cannot remap the software interrupt exception vector. 

Does this mean that any SVC calls will stall while I am programming bank0? 

Is there any way around this? 

Regards,

Mathieu

  • 0
    TI__Guru**** 190846 points

    Hi Mathieu,

      Your understanding is correct that SVC call may have unpredictable behavior because you don't have a proper vector for SVC. The question is why you will have active SVC call or any exception in the first place. If you are doing a program/erase then you should disable all exception from happening. The SVC routines might be in bank0 as well that you don't have a handler to handle the call as the bank0 being programmed or erased. 

  • 0 in reply to Charles Tsai
    Intellectual 440 points

    Hello Charles,

    Thanks for your answer. The idea was to support in system programming  while keeping the application functional by having two identical software images, one stored in bank 0 and the other one in bank 1. I could then run on image 1 while updating image 0. I understand that is not possible.

    Mathieu

  • 0 in reply to Mathieu Patte
    Intellectual 440 points

    Actually, it seem I can relocate the exception vectors to internal RAM using the POM.

    Has someone actually attempted this? 

    Mathieu

  • 0 in reply to Mathieu Patte
    TI__Expert 6985 points

    Mathieu,

    The POM module isn't meant to be used in that way, it is considered to be a debug module used during development and not as safety related.
    Also, if you would use it in the way you described you would most likely see some issues.

    Best Regards,
    Christian

  • 0 in reply to Christian Herget
    Intellectual 440 points
    That's too bad. It looked like an elegant solution to my problem.
    Any idea of the kind of issues we could encounter?

    Mathieu
  • 0 in reply to Mathieu Patte
    TI__Expert 6985 points

    Mathieu,

    Unfortunately I think that there is no "elegant" solution to this. The best you could do is to not overwrite / erase flash sector 0 and to use a small SW routine to redirect the exceptions to the active firmware image. This would be similar to what should or can be done with a bootload residing in sector 0.
    Another thing you could do is to swap the RAM and Flash start addresses (BMMCR1), with this the Exception Vectors would be in the RAM. However, this will be a complex thing.

    About the issues with using POM, this is from the device TRM:

     6.9.4   POM Overlay Considerations

     •    The POM overlay can map onto up to 8MB of the internal or external memory space. The  starting address and the size of the memory overlay are configurable via the POM module control registers. Care must be taken to ensure that the overlay is mapped on to available memory.

    •    ECC must be disabled by software via CP15 in case POM overlay is enabled; otherwise ECC errors will be generated.

    •    POM overlay must not be enabled when the flash and internal RAM memories are swapped via the

    MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).

    •    When POM is used to overlay the flash onto internal or external RAM, there is a bus contention possibility when another master accesses the TCM flash. This results in a system hang.

    –   The POM module implements a time-out feature to detect this exact scenario. The time-out needs to be enabled whenever POM overlay is enabled.

    –   The time-out can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global

    Control register (POMGLBCTRL, address = 0xFFA04000).

    –   In case a read request by the POM cannot be completed within 32 HCLK cycles, the time-out (TO) flag  is  set  in  the  POM  Flag  register  (POMFLG,  address  =  0xFFA0400C). Also,  an  abort  is generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a data fetch.

    –   The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM module is set. If so, then the application can assume that the time-out is caused by a bus  contention between the POM transaction and another master accessing the same memory region. The abort handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been caused due to a time-out from the POM.

    Best case it will work, worst case you will see "random behaviour", which I guess is not an option.

    Best Regards,
    Christian

  • 0 in reply to Christian Herget
    Intellectual 440 points

    Many thanks for the elaborate answer Christian. 

    Effectively, it seems like a bad idea to use the POM the way I intended! 

    Just a quick question about your first idea about having a redirection of the exception vectors. Would that actually work? Wouldn't any exception stall when for instance erasing another sector in bank 0? 

    Mathieu

  • 0 in reply to Mathieu Patte
    TI__Expert 6985 points
    Mathieu,

    For sure, you are right this wouldn't work if you are operating on bank 0.
    You should see an abort if you would try to do so, was my fault.

    Best Regards,
    Christian
  • 0 in reply to Christian Herget
    Intellectual 440 points
    ok, thanks for the clarification.
    I will find another way.

    Mathieu