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RM48L952ZWT: ADC Clock Timing

Sarah Weinberger
Expert 1915 points
Other Parts Discussed in Thread: HALCOGEN

Am I correct that in order to accomplish the following ADC clock timing request?

1.6.2. Configure the ADCLK frequency to VCLK/32 by writing 0x0000001F to the clock divider into the Clock Control Register (ADCLOCKCR at 0xFFF7C008). Note that VCLK was previously set to the oscillator frequency (20MHz) divide by 2, or 10Mhz.

that I have to set the Cycle Time in the ADC1 Configuration to 3200 ns.

Here is my thinking.  VCLK1 timing is 10 MHz. The request is to make that VCLK/32 or 0.3125 MHz, which I converted to 0.0000032 seconds. Multiplying by 1000*1000*1000, gets me 3200 ns, hence the entry above.

I already changed the clock speed to 20 MHz from the default 16 MHz, as shown here in the Clk Source tab.

  • 0
    TI__Guru**** 190806 points
    Sarah,
    I can only tell you that your HalCoGen configuration is matching the EE's comments to configure ADCLK=VCLK/32. As far as why your application wants to use a slow VCLK at 10MHz and an even slower ADCLK I think your application needs to decide. The HCLK for which is the system clock is running at 20MHz using OSC. The device can run up to 220MHz and you are running at a much reduced frequency not taking advantage the device's performance.
  • 0 in reply to Charles Tsai
    Expert 1915 points
    Hi Charles, hmm, I did not know that the device could run up to 220 MHz, nice to know, not that I have any say in the slightest on speed, but I will pass the comment on to the EE.

    That is a good comment; thank you. I did code the original version of the software on the Intel 80386EX and I can tell you that performance matters, as the software does a lot. There are multiple cooperative threads, not to mention interrupts, so a higher performance is best. I would use 220. I sent the comment to the EE, so we shall see.
  • 0 in reply to Sarah Weinberger
    TI__Guru**** 190806 points
    Hi Sarah,
    Yeah, let's wait for your EE to confirm so what is the intended operating frequency so the ADCLK and ADC sample time can be adjusted accordingly.