RM48L952ZWT ADC Clock Sample Time Verification

I saw the tool-tip that the Sample Time is in ns. The value of 4096.00 threw an error upon save, which wound up at 200, presumably the maximum.

VCLK is 10 MHz, which corresponds to 100 ns, if I remember correctly. One clock period is one Hz, which means that 100 ns is one clock period. The requirement is 4096 clock periods, so would that make 40.96 as the sample time?

Something is not right. I really suggest that you talk with your EE on what they meant in the comments and if that is what they want. Does he mean 4096ns or 4096 cycles? It is a huge difference. You have already configured the ADCLK to be 3200ns in your other post. If you want 4096 cycles for the sampling time it means 4096*3200= 13ms. I don't think this is what you want. 4096ns looks more like it.

According to the manual,

the sampling window time is

SW = G1 ACQ + 2 in terms of ADCLK cycles.

The requirement is:

1.6.3. Configure the acquisition time for the ADC1 group by writing 0x00000FFE to the AD Sampling Control Register (ADG1SAMP at 0xFFF7C064). This sets the acquisition time to 4096 ADC clock periods.

The value 0xFFE translates (I used a calculator) to 4094.

SW = "G1 ACQ" + 2 ADCLK cycles

       = 4094 + 2 ADCLK cycles

       = 4096 ADC clock periods, when you equate cycles to periods.

I generated the code with the sampling time shown here and the resultant code.

and the resultant code:

Notice that HalCoGen set the sampling window size to zero, not 4096 clock cycles.

adcREG1->G1SAMP = 0U;

I just checked and the only fields HalCoGen allows users to modify in the second from the bottom group is "Enabler Sampling Capacitor Discharge" and "Sampling Time".

HalCoGen wants ns, not ADC clock cycles, so:

ADCLK = VCLK/32 = 10MHz / 32 = 0.3125 MHz.

Using  "calctool.org/CALC/other/converters/freq" as my conversion tool, yields 3200 ns for a frequency of 0.3125 MHz. That means that one clock period is 3200 ns. HalCoGen wants ns, not clock cycles, so the value in the sampling time should be 4096 ns, a factor of 1.28 more than the ADC clock cycle, weird choice. I entered 4096 and get zero, as shown above.

Thoughts?

Sarah,
You entered 40.96ns in the field. This is smaller than even one ADCLK which is equal to 3200ns in your setup. Let's say you want a total 9600ns of sample window. Since one ADCLK is 3200ns, you will need 3 ADCLK to cover 9600ns. As you have seen the equation below,
SW = G1 ACQ + 2 in terms of ADCLK cycles

The G1 ACQ needs to be 1 as 2 ADCLK is the minimum that is always needed. If you put 9600 into the field then you will see sample presscaler field changed to 1. Once you generate code you will see a 1 written to G1SAMP register.

This is why I'd like to know if you want 4096ns as the sample window or 4096 ADCLK cycles as the sample window as 4096*3200us is 13ms which is very long.

Hi Charles,

I just wrote the EE, so we shall see what he responds. Here is what I wrote:

"What size do you want for the ADC sample window? Do you want the sample window to be 4096ns or 4096 ADCLK cycles? 4096 ADCLK clock cycles equates to 4096*3200us or 13ms, which is very long."

I borrowed what you wrote me and changed a few words.

Sarah