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Looking for idea of 64 channels generator

Auger
Prodigy 40 points

Dear members, 

I need ideas for a generator. It's requirements:

  • 64 channels sinusoidal ~60cycle burst, frequency 27-40 kHz;
  • every channel should have possibility to have ~50uS delay;
  • output voltage under 1V

The first problem what I faced that common microcontrollers have under 2 ADC. But after that I had an idea to connect ADC over I2C, but not sure if uC can handle it: 64 channels, 8 bit resolution, 100 kHz sampling - 50 MB/s data flow. 

Another idea to use field programmable gate arrays... but I am not familiar with that.

Do I need 32 units of microcontrollers? How can I make this work simpler?

Thank you,

Auger

  • 0
    Guru 10570 points
    You refer to generator and ADC. Are you using both?


    Do you need simultaneous triggering?

    Robert
  • 0 in reply to Robert Adsett72
    Guru 117855 points

    Sixty-four generator channels and imprecision introduced w/ADC, over I2C, and (break-through) "50MB/s data flow."

    It appears that more than poster's "first identified problem" lurk.   And the "2 ADCs" poster notes may contain over 20 analog channels - confusion & imprecision appear rampant...

    Would it not prove useful to search the specs & descriptions of the nearest performing, commercially available, instruments?

    And - armed w/that - if "64 channels" (really) is needed might a, "Scaled Array" of MCUs (perhaps each providing a (more realistic) 16 such channels - proves (far) more, "achievable/real-world accommodating?"

  • 0
    TI__Guru**** 244400 points
    Hello Auger

    I agree with Robert: Output voltage under 1V and ADC?

    Regards
    Amit
  • 0 in reply to Robert Adsett72
    Prodigy 40 points

    To Robert: I need a sinusoidal signal, so I think to use digital to analog converter. 1V is for our piezo crystals array what I need to excitate.  

    Sorry for mixing of terms.

  • 0 in reply to Auger
    Guru 11940 points

    1V is for our piezo crystals array what I need to excitate.

    Piezos I know are more like tuning forks, and oscillate on a frequency determined by size...

    However, I suggest to not ignore cb1's comment. 50 MB/sec. is quite heavy, I even suggest it is out of the range a single Cortex M4 can handle properly.

    I know of no general-purpose MCU with more than 2 DAC channels. And only internal channels would allow you to output a continuous data stream (i.e. sinusoidal signal) without CPU load. External DACs require more CPU load, even when managing the serial communication to the DACs via DMA. Real-time changing frequency and waveform will be a real challenge.

    If you really need 64 channels, the DAC will have a major impact on the BOM. In this case, you could split them in sections and have, for instance, one M0 or M3 core managing 16 channels. Anyway, it is surely getting complex.

  • 0 in reply to f. m.
    Guru 47900 points

    f. m. said:
    you could split them in sections and have, for instance, one M0 or M3 core managing 16 channels.

    Indeed f.m. - you have seconded my direction that "Scaling" - and only scaling - is this poster's ticket to (possible) success.

    Data rate remains unaddressed - and troubling.  

    And the refusal (or silence) to investigate the commercial efforts of others would cause investors to "pass."

  • 0 in reply to cb1
    Guru 11940 points

    And the refusal (or silence) to investigate the commercial efforts of others would cause investors to "pass."

    The possibility remains that the intended device is not "commercial" (i.e. for sale), but for internal or lab purposes, where costs and BOM play a secondary role.

    Data rate remains unaddressed - and troubling.

    But we agree that the general function of the device, or more specifically the O.P.'s current idea thereof, seems troubled, and not yet fully thought-out.

  • 0 in reply to Auger
    Guru 27665 points
    OK, so no A2D

    Still unanswered is whether you need simultaneous triggering/updating. The 50uS delay requirement suggests you might.

    As f.m. and cb1 have also suggested this is going to require external D/As and thus an interface to them.

    My inclination would be to use an FPGA with a micro to control it. Alternatives include FIFO fed DACs clocked from a micro, analog generation with micro control, DSP with dedicated high speed DAC support ......

    You'll have to determine what you need and what you are capable of working with.

    Robert
  • 0 in reply to f. m.
    Guru 27665 points

    f. m. said:
    And the refusal (or silence) to investigate the commercial efforts of others would cause investors to "pass."

    The possibility remains that the intended device is not "commercial" (i.e. for sale), but for internal or lab purposes, where costs and BOM play a secondary role.

    Grad students are free

    f. m. said:
    Data rate remains unaddressed - and troubling.

    But we agree that the general function of the device, or more specifically the O.P.'s current idea thereof, seems troubled, and not yet fully thought-out.

    There's a lot of detail to be considered. This appears to be at the "I wonder if..?" stage. As a sanity check on general capabilities it's not bad as a product spec it needs a lot of work.

    Robert

  • 0 in reply to Robert Adsett
    Prodigy 40 points

    Thank you guys for the discussion. This would be lab equipment for my dissertation.  A delay would be used for ultrasound beam focusing. We will use only resonant frequency, the range only for possible frequencies.

  • 0 in reply to Auger
    Guru 47900 points
    Really - the intended usage bears little upon, "Proper investigative techniques - Speeding, Easing & Enhancing - your design efforts."

    Those coming before you - entering the marketplace - most always will have, "covered the major bases - and provide "stepping-stones" toward your success. Turning your back on prior art - previous success - proves (almost always) unwise & short-sighted...
  • 0 in reply to Auger
    Guru 10570 points
    I thought it might be something like that. This is more research than development.

    Although I said grad students are free and it's a common attitude it is in your interest to avoid going down a rabbit hole of detailed development rather than concentrating on your research effort. The trouble may be lack of resources.

    Nonetheless, I'm going to assume you either have some resources or can pitch some of this as general purpose lab equipment with use beyond this project. Sometimes new equipment opens new possibilities.

    The first thing I'd try is to find an instrument that had the builtin capabilities you need.

    Assuming they are unavailable I'd take a look at NI and Labview. While there's a lot I don't like about them this kind of one off lab instrument is their strength. The compact RIO line form factor fits your application but it may not have the performance. Talk to an NI application engineer and get their recommendations. Unfortunately NI is not known to be inexpensive but they do have educational discounts.

    Robert
  • 0 in reply to Robert Adsett72
    Guru 117855 points

    Robert Adsett72 said:
    The first thing I'd try is to find an instrument that had the builtin capabilities you need.

    And that's just what I've called for - twice now.   Turning one's back on "existing art" is fool-hardy - and my firm's finding is that (most) grad students have vastly underdeveloped "investigative skills" - and little desire to improve.   In industry - this "eats" time/money - never good.

    Review of NI & Labview surely should be one facet of an "investigation" - there are many - and key/critical approaches/methods may be uncovered with minimal investment of time & effort...   (and "rabbit hole" extraction usually is greatly reduced - sometimes eliminated - thru investigation...)

  • 0 in reply to Auger
    Guru 10570 points
    A thought, since you are driving a resonant structure consider if you can drive it with a square wave or a square wave followed by a filter to reduce high order harmonics. The resonant structure will help filter to the primary frequency. Square waves are a lot easier to generate than clean sine waves.

    Robert
  • 0 in reply to Robert Adsett72
    Guru 11940 points

    Square waves are a lot easier to generate than clean sine waves.

    ... and would allow one to use simple hardware like PWM driver circuits (anybody remembering the TTL "graveyard" boards of the '70 and '80 electronics ?). Or, even better (smaller, higher scalability, etc.), a FPGA.

  • 0 in reply to f. m.
    Guru 27665 points
    Exactly what I was thinking. A whole range of options open up using fairly slow digital logic.

    And with a decent FPGA the micro 'only' has to deal with management issues. Most of the timing has been moved to the FPGA.

    Robert