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HET and GCLK

Robert Kalmar
Prodigy 30 points

Hi, I want to decrease the power consumption of the TMF470MF06607 microcontroller but at the same time I need the HET module to be running.


My idea was to turn off the all the clock domains (GCLK, HCLK, VCLK and AVLCK) except of VCLK2 (driving the HET) and RTICLK. The problem is that in this case the HET looks to be running but the signal generated is not valid. I identified that the problem is in the GCLK domain. If I let it running and just turn the M3 core off (using WFI instruction) the HET works fine. Of course with the GCLK also the HCLK domais stays running.

Is it expected behaviour? According the clock distribution the HET module shall be independent of GCLK domain.

Thanks Robert.

  • 0
    TI__Guru 68830 points
    Robert,

    Yes although I can't exactly explain why other than to say that the two low power modes that the device supports:

    DOZE
    SLEEP

    both are defined to have both GCLK and VCLK2 turned off together.

    Would need to dig into your setup and try to figure out why you are getting the lower freq. clock on VCLK2 - maybe you are setting the source back to the OSC before turning off GCLK?

    Anyway the WFI is the expected way to turn off most of the logic power (used by the CPU) while the HET keeps running. Not turning off GCLK.
    Should give you about the same power reduction anyway.
  • 0 in reply to Anthony F. Seely
    Prodigy 30 points
    Anthony,
    the problem was as you suggested. I was turning back the VCLK2 source to oscilator in "GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC)".

    Thank you,
    Robert