I have some feedback and questions regarding the recently released revision of the TM4C129x errata.
Appendix 3
First off, Appendix 3 is very difficult to use. It's not easy to copy multiple pages of text out of a PDF and when you do all the indentation is missing. The 6 pages of replacement for SysCtlClockFreqSet is particularly bad, especially given that the real change was just adding 7 lines. Here's a diff so we can easily see the changes we're discussing.
5 lines appear to have been unintentionally deleted from SysCtlClockFreqSet. Can you confirm that this is the case and that there were not also supposed to be changes in that area?
//
// If the loop above did not timeout then switch over to the PLL
//
if(i32Timeout)
{
ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG);
ui32RSClkConfig |= ((ui32SysDiv - 1) <<
SYSCTL_RSCLKCFG_PSYSDIV_S) | ui32OscSelect |
SYSCTL_RSCLKCFG_USEPLL;
ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU;
//
// Set the new clock configuration.
//
HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig;
}
else
{
- ui32SysClock = 0;
- }
- }
- else
- {
//
// Set the Flash and EEPROM timing values for PIOSC.
//
HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(16000000);
Next, there is a bug in the code that checks if the PLL is already configured. The Q field in PLLFREQ1 is now being set to 1 rather than 0 so this check needs to be updated as follows.
//
// If there were no changes to the PLL do not force the PLL to lock by
// writing the PLL settings.
//
if((HWREG(SYSCTL_PLLFREQ1) !=
- g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1]) ||
+ g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1] |
+ g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][2]) ||
(HWREG(SYSCTL_PLLFREQ0) !=
(g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] |
SYSCTL_PLLFREQ0_PLLPWR)))
{
bNewPLL = true;
}
else
{
bNewPLL = false;
}
Finally, any idea when TivaWare 2.1.3 will be released?
SYSCTL#22
This errata says that PSYDIV may not be loaded:
When generating system clock from the PLL, the user programs the system control register bits RSCLKCFG.PSYSDIV to divide the PLL output. This register value may not be loaded into the physical divider causing the system clock to be divided by 2.
The workaround sets PLLFREQ1.Q to 1, which results in a division by 2 up front, and then uses a smaller value for PSYSDIV. I don't see how that would resolve the issue if PSYDIV was indeed not being loaded. Perhaps the errata should say Q rather than PSYSDIV?
Do you have any additional information about the conditions where the divider isn't loaded? As far as I know my clock isn't off by a factor of 2.
For some crystal values, the up-front division by 2 results in a results in a reference frequency outside the range of 4 to 30 MHz given in data sheet (table 5-7, footnote b). For example with a 25 MHz crystal you get 2.5 MHz after division by 5 and 2. Has this been considered?
