PBIST in TMS570LC4357

Sindhu,

I split this into it's own thread with PBIST in the title.

Some of the memories that get tested are 2 port. See 2.2.4.1 PBIST RAM Grouping and Algorithm Mapping For On-Chip SRAM Modules far right hand column.

I can't answer DWR, SMS, PLS or RLS as these are not documented. I'll file a CQ against the TRM to get this clarified. SDOCM00122186 is the ticket #.

Thank you Anthony...

Meanwhile knowing about those bits, I saw the Faults that can be detected using March13 Algorithm are
– Address decoder faults
– Stuck-At faults
– Coupled faults
– State coupling faults
– Parametric faults
– Write recovery faults
– Read/write logic faults

Similarly what are the faults that can be found using Triple_read_slow_read and Triple_read_fast_read algorithms used for ROM testing?

Hi Sindhu,

I think it's going to be most of the same but not the 'write'.

The triple read does:

1. Fast sequential checksum
2. Slow reverse sequential checksum (reads each location 2 or 3 times but sums only the last read)
3. XOR checksum (read address 0 then N-1 then 1 then N-2…)

If you want more details the best place to go is the www.ti.com/safetyanalysis where you get the manual and FMEDA tool.

The reason to test these ROMS is that they are used by the BIST controllers, (ex. STC.) So if there is a problem in the ROM, then you
cannot be sure of the effectiveness of the later testing that relies on the ROM such as logic BIST of the CPU.

-Anthony

Anthony, thank you for sharing the link. This is will be of great use but the website asks for NDA agreement from the company with TI. I'm learning the microcontroller independently and couldn't download the Document and FMEDA tool. Is there an alternate solution for this? But I'm completely interested in reading the manual.

In PBIST, I do have another doubt. When I run test for STC and PBIST ROM, what indicates that fault occurred in a particular ROM(out of the bits that I've listed next)?

Fail Status registers FSRF0 or FSRF1.
RAMT register that indicates the RGS and RDS values of the failure RAM.
FSRC0 and FSRC1 registers that contain the failure count.
FSRA0 and FSRA1 registers that contain the address of first failure.

I have this doubt since FSRF 0 or 1 indicates the Ports of RAM... So please explain to understand this.

Thanks in advance.

Hi Sindhu,

There isn't an alternative to the NDA and the safety manual online is an abbreviated version of the actual manual.
The NDA is simplified however - not a typical negotiation process.

I am not sure about the answer to your questions ... I would assume that if the memory has only a single port it would result in fail status in the '0' register.  and if it's a 2 port a fail on the 2nd port would show up in the FSR1 register.

But that isn't documented

Best Regards,

-Anthony

Hi, 

We are using the same TMS570LC4357. When we execute the PBIST, it FSRF0 indicates failure and FSRF1 indicates no failure. can i confirm that the there is only one RAM port from this? or some error actually is occuring on one of the two ports?

I checked PBIST on two launchpads. both are failing on port 0. while on TMS570LS3137, there is no failure.

Thanks,

Sharif