• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 30 subscribers
  • Views 1333 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TM4C129 SSI Freescale Protcol

SL
Intellectual 410 points

Hi,

We have a question with regards to the Fss pin.  We are using Freescale SPI Frame Format 3 and according to the datasheet, for continuous back-to-back, the Fss pin remains active low.  How does the uC know that this is a continuous back-to-back transmission versus a single byte?  Since Format 3 is not allowed for use with the advanced mode, then we can't use the advanced API SSIAdvDataPutFrameEnd to signal the end of frame for the FSS signal to be de-asserted.

Thanks.

  • 0
    TI__Guru**** 244400 points
    Hello SL,

    At the end of the byte being sent out of the serial shift register, if there is another byte available in the FIFO, then it will use the continuous mode for back-to-back transmission.

    Yes, you are correct. Mode 3 is not supported in Advanced Modes. Only Mode 0 shall work for Advanced modes.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Intellectual 410 points
    Hi Amit,

    How can we accomplish this? It looks like once we use the SSIDataPut, the data gets shifted right away before we can put another byte into the FIFO for the continuous mode.

    Thanks.
  • 0 in reply to SL
    TI__Guru**** 244400 points
    Hello SL

    It depends on the input and output rate. if the output rate is 100 KHz for a 8-bit data, then if the CPU can write to the FIFO in less than 8/100Khz or 80us, every time, then it would be continuous back-to-back transfer.

    However if that is not possible, then the FSS must be controlled as a GPIO such that the CPU will make the pin Low and High as per the data transfer requirements

    Regards
    Amit