Hi all,
In an earlier thread, I asked about SYSESR bit 6 on RM57L843. The Technical Reference Manual, spnu562, says that it is "reserved", while HL_system.c marked it as CPU1_RESET.
The response I got in that thread is that SYSESR bit 6 is a reserved bit.
device family is designed for both lockstep and dual-core (not locked). The RM57L843 only supports single core mode (lockstep) but the header is sort of preparing for an unlocked device. no plans to release an unlocked device at this time though. anyway just ignore this and treat CPU1 reset as reserved.
Therefore I removed it from my reset handler.
However, today I looked at SYSESR and found that this bit was set.
SYSESR == 72 == 0x48 == 1001000 == Bit3 + Bit6 == EXTRST + (??? Reserved ???)
I was expecting the EXTRST, but was not expecting Bit6.
It behaves like any other reset flag; it persists between soft resets (not PORRST) and writing 64 to this register clears Bit6, as advertised. There does not seem to be any way of setting Bit6 in software. So, the hardware must have set it. I thought it was a reserved bit that does not indicate any particular kind of reset.
Can you provide any insight on how Bit6 may have gotten set, and confirm whether my reset handler needs to care about Bit6?
Thanks,
Peter
