Other TI processors provide header files with peripheral structures consistent with the documentation down to the bitfields. As an example DSP2833x_ECan.h defines all the registers down to the bits
/* eCAN Master Control register (CANMC) bit definitions */
struct CANMC_BITS { // bits description
Uint16 MBNR:5; // 4:0 MBX # for CDR bit
Uint16 SRES:1; // 5 Soft reset
Uint16 STM:1; // 6 Self-test mode
All I can find for the Hercules device support are files like reg_can.h and garbage code using hard coded values for the bits.
typedef volatile struct canBase
{
uint32_t CTL; /**< 0x0000: Control Register */
example from SPNA131
if (node->IF2MCTL & 0x4000U)
I'm looking for either register definitions down to the bit level or at least bit level masks consistent with the data sheet.
if (node->IF2MCTL.bit.MSGLST) // Header file defines structures down to bit level.
if (node->IF2MCTL & MASK_MSGLST) // Header file defines bit masks.
As a long time TI developer, we went through this years ago with other processors (C54, C6x, etc..). Initially masks were provided, then structures with .all and .bit. Is the Hercules a big step backwards or do header files consistent with the documentation exist somewhere I haven't found?
P.S. HALCOGEN is the lazy answer, but it's not a real solution. Hard coded values in source file is hard to code review, prone to erors, and not a good practice.
