Using a TM4C129 variant.
I want to use the EPI to access a 1Mx16bit external static RAM and one other device that is not relevant to this question.
So I am planning to use Host Bus mode 3 (ALE with two chip selects), BSEL 1 (separate bytes)
I would like to verify which half of the data bus BSEL0n and BSEL1n correspond to.
The processor is configured for Little Endian.
The docs indicate that BSEL0n corresponds to the LSB of the bus.
My assumption is that BSEL0n is asserted when accessing D8 - D15 and BSEL1n is asserted when accessing D0 - D7.
Is this correct?
