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tms570 ESM Status Register is an array?

cc liu
Expert 1150 points
Other Parts Discussed in Thread: HALCOGEN

Dear Experts

According to the code generated by Halcogen, the esmBase looks like

typedef volatile struct esmBase
{
uint32 EEPAPR1; /* 0x0000 */
uint32 DEPAPR1; /* 0x0004 */
uint32 IESR1; /* 0x0008 */
uint32 IECR1; /* 0x000C */
uint32 ILSR1; /* 0x0010 */
uint32 ILCR1; /* 0x0014 */
uint32 SR1[3U]; /* 0x0018, 0x001C, 0x0020 */
uint32 EPSR; /* 0x0024 */
uint32 IOFFHR; /* 0x0028 */
uint32 IOFFLR; /* 0x002C */
uint32 LTCR; /* 0x0030 */
uint32 LTCPR; /* 0x0034 */
uint32 EKR; /* 0x0038 */
uint32 SSR2; /* 0x003C */
uint32 IEPSR4; /* 0x0040 */
uint32 IEPCR4; /* 0x0044 */
uint32 IESR4; /* 0x0048 */
uint32 IECR4; /* 0x004C */
uint32 ILSR4; /* 0x0050 */
uint32 ILCR4; /* 0x0054 */
uint32 SR4[3U]; /* 0x0058, 0x005C, 0x0060 */
} esmBASE_t;

my question is  SR1 and  SR4 are both array with three elements?

so what SR1[0] SR1[1] SR1[2]   represents respectively?  same problem with SR4 

and in the SPNU517B

there should be SR2  and SR3, but not in the code.

and in the halcogen, in esm tab, the group2 and 3can not be clicked(button in grey) , so does that mean the group2 and 3 can not be configured at all?  or I have to configure them by coding manually?

Thanks for the answering.

Leo

  • 0
    TI__Guru**** 191906 points

    Hi,

      SR1[0] is the ESM group1,  SR1[1] is the ESM group2 and SR1[2] is the ESM group3. 

      SR4[0] is the ESM group1 from channel 32 to 63 while SR1[0] is for ESM group1 from channel 0 to 31.

      There is nothing to configure for group2 and group3. You can't disable them.

  • 0 in reply to Charles Tsai
    Expert 1150 points
    Hi Charles
    So the SR4[1] and SR4[2] are useless?
    Leo
  • 0 in reply to Charles Tsai
    Expert 1150 points
    And for each bit, does it correspond to whether each channel interrupt enable or not?
    Leo
  • 0 in reply to cc liu
    TI__Guru**** 191906 points
    Hi Leo,
    The SRx registers are the status registers, not control registers. Each bit in a register indicates the status of the channel. For example, if SR1[1]=0x4 then it means there is a CCMR4 compare error. Please refer to the your respective device datasheet on the ESM channel assignment table where the CCMR4 compare error is mapped to Group2 channel 2. If SR1[2] = 0x8 then it means that there is a RAM ECC uncorrectable error as the RAM ECC uncorrectable error is mapped to Group3 channel 3. If SR4[0] = 0x8 then it means that Group1 channel 35 has detected an error which is FMC correctable error. The SR4[0] covers channel 32-63 of group1 while SR1[0] covers group1 channel 0-31. Hope this is clear now.

    You cannot enable or disable channels in group2 and 3. They are always enabled as these two groups are considered severe that requires application attention. Only group1 can be enabled or disabled. For example, You will need to use the ESMIESR1 register to enable the channels in Group1. Please refer to the corresponding TRM of your device.
  • 0 in reply to Charles Tsai
    Expert 1150 points
    Charles
    Thank you for your answer. It solved my question and was verified.
    All the best
    Leo