RM48L952ZWT: Setting up a timer

Charles, The example is a bit confusing for setting up a timer, 2 in my case, that does NOT start using RTI1 Compare | Compare 0 Period. I believe that I am fine with the GUI part of the configuration, but am a bit unsure about the sys_main part of the coding.

Before going on, I have a question regarding the example. Here is a screenshot of the example:

Notice the example says "Map VIM Channel 2 to IRQ," however the screenshot shows VIM Channel 2 mapped to FIQ, not IRQ. Which one is it? (Please have the document team correct the bug.) Does this bug affect the settings that I made, see screenshot below?

Here is my VIM Channel 0-31 configuration:

Here is my RTI1 Compare configuration:

Do I need to do anything else in the sys_main module (or anywhere else)?

	// Initailize: VIM Table
	vimInit();
	vimChannelMap(9, 2, &gioHighLevelInterrupt);
	vimChannelMap(2, 3, &rtiCompare0Interrupt);
	vimChannelMap(64, 4, &sciHighLevelInterrupt); // COM1 RX: SCI Level 0, which makes it Interrupt Request 64
	vimChannelMap(13, 5, &linHighLevelInterrupt); // COM2 RX: LIN/SCI Level 0, which makes it Interrupt Request 13
	vimChannelMap(74, 6, &sciLowLevelInterrupt); // COM1 TX: SCI Level 1, which makes it Interrupt Request 74
	vimChannelMap(27, 7, &linLowLevelInterrupt); //COM2 TX: LIN/SCI Level 1, which makes it Interrupt Request 27

	// Initialize: RTI
	//
	// Initialize RTI driver.
	rtiInit();

	// Enable RTI Compare 0 interrupt notification.
	rtiEnableNotification(rtiNOTIFICATION_COMPARE0);

	// Enable interrupts
    //   - Clear I flag in CPS register
	//   - Note: This is usually done by the OS or in an svc dispatcher
	_enable_IRQ();

	// Start RTI Counter Block 0.
	rtiStartCounter(rtiCOUNTER_BLOCK0);

My goal is to set up a 10ms timer on Counter Period 1 and a 100ms timer on Counter Period 2, as shown in the above screenshot.

Am I correct that "Compare 0-3 Periods" are all part of Counter Block 0?

Is the notification code correct?

/* USER CODE BEGIN (8) */
/* USER CODE END */
#pragma WEAK(rtiNotification)
void rtiNotification(uint32 notification)
{
/*  enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (9) */
	// Fire CCM 10ms timer event: System, Algorithm, and Application Stuff.
	if (rtiNOTIFICATION_COMPARE1 == notification)
		TimerIsrCombined();
	else if (rtiNOTIFICATION_COMPARE2 == notification)
		TimerIsrWatchdog();
/* USER CODE END */
}

Hi Charles,

Great catch! I set up the first RTI interrupt, merely because the interface specification called for it:

1.7. Real Time Interrupt- Setup a real time interrupt every 100msec.

1.7.2. Set the time period of the RTI interrupt by writing 500000 to RTICOMP0 at 0xFFFFC050. This will cause 500000 (decimal) prescale clocks (which is VCLK/2, set in the next section) to generate the RTI, when enabled.

1.7.3. Set the count value to be added to the RTICOMP0 register when it hits the compare value in RTICOMP0 by writing 500000 to RTIUDCP0 at 0xFFFFC054.

1.7.4. Set the prescale count by writing 1 to RTICPUC0 at 0xFFFFC018, which will cause the Upcount 0 prescale counter to divide VCLK by 2, to increment the RTIFRC0 counter. Thus VCLK is divided by 1000000. And VCLK is the 20MHz oscillator divided by 2, which means you get a RTI every 100 msec.

1.7.5. Select RTICOMP0 as the register that RTIFRC0 (the free running counter) is compared to by writing 0 to RTICOMPCTRL at 0xFFFFC00C.

1.7.6. Write 0 to RTITBCTRL at 0xFFFFC004, to select RTIUC0 to clock RTIFRC0 instead of the Network Timing Interface.

1.7.7. Write 1 to RTIGCTRL at 0xFFFFC000, to start the RTI counter chain.

1.7.8. Write 0x00010000 to RTISETINTENA at 0xFFFFC080, to enable the RTI interrupt.

What the specification failed to do was answer the question why! To my knowledge, there are two timers: one for the watchdog (100ms) and the second to periodically read values from the ADC. There are GPIO line signals for the ACOK and BUSOK signals, but that is something else entirely. I deleted the 2nd timer, as and re-purposed the zeroth timer to be the watchdog timer. That changes the VIM table to:

// Initailize: VIM Table
vimInit();
vimChannelMap(9, 2, &gioHighLevelInterrupt); // GPIOA Interrupts (BUSOK), see 1.3.2 (GIOA[0] BUSOK), 1.8.4.1 in interface specification, and GIO tab bit 0
vimChannelMap(23, 3, &gioLowLevelInterrupt);  // GPIOA Interrupts (ACOK), see 1.3.3 (GIOA[1] ACOK), 1.8.4.2 in interface specification, and GIO tab bit 1
vimChannelMap(2, 4, &rtiCompare0Interrupt); // Timer: Watchdog
vimChannelMap(64, 5, &sciHighLevelInterrupt); // COM1 RX: SCI Level 0, which makes it Interrupt Request 64
vimChannelMap(13, 6, &linHighLevelInterrupt); // COM2 RX: LIN/SCI Level 0, which makes it Interrupt Request 13
vimChannelMap(74, 7, &sciLowLevelInterrupt); // COM1 TX: SCI Level 1, which makes it Interrupt Request 74
vimChannelMap(27, 8, &linLowLevelInterrupt); // COM2 TX: LIN/SCI Level 1, which makes it Interrupt Request 27
vimChannelMap(3, 9, &rtiCompare1Interrupt); // Timer: Combined

Thanks again for the catch. I will have to ask the EE if he wanted the RTI to do something other than what I know to do. If so, I can add that logic to the watchdog timer, same interval.

asdf