Hi All
I saw there is something called common mode impact in CCM module?
so what is that ? and why the signals of the CPUs to be compared are temporally diverse? both of them ? diverse means the invert of electrical level？
why we need two cycles delay of the input into the Checker CPU?
Many thanks
leo
Hi Leo,
Common mode failure means that a failure can happen to both the CPU and the checker CPU and the CCM is unable to detect any difference between the two CPUs. For example, a voltage that is out of range can be considered as a common mode failure. If the voltage drops below the spec that can create speed path problems on the chip, then both CPUs may be reading the same bad data from the memory. Since both CPU are reading the same bad data, the CCM is unable to detect any difference. Nevertheless, both CPU can be in unpredictable state due to the bad data, i.e. reading invalid instructions from the flash.
To address common mode failure, the CPU during implementation phase are designed to be as different as possible. We are talking about at the chip design layout level such that a failure is not likely to cause both CPUs to fail with the identical results. This is what we meant by diverse.
Clock is another common mode failure. If there is only one common clock that is fed into both CPU then if the clock is bad (too slow or too fast) then both CPU may continue to operate identically and the CCM will not be able to detect the difference. To mitigate this, we create two different clock trees with each for one CPU. Not only we create two different clocks,all signals that go to the checker CPU are first delayed by two cycles. This create some offset in timing between the two CPUs. The outputs of the primary CPU are then delayed two cycles again before it is compared to the checker CPU. See diagram below.
Please go to your respective device datasheet section that talks about dual core implementation for further details.
