Sharing external RAM with DSP (f28377S) via EPI - EMIF

Hello PAk,

No. This is not a workable solution for EPI of TM4C and EMIF of C2000 device to be connected to the same SDRAM. Electrical bus contention would be there. A small dedicated RAM would be more suitable

Other than there are complex switching logic if a external memory shared device is to be implemented.

SDRAM are rather very cheap and come in small form factor. So having 2 of them on the same board would not be an issue.... Forum inputs!!!

Regards
Amit

Thank you Amit. I see.

The point was to share memory, (and a fast communication way between them), not just adding some RAM.
Do you recommend anything else than the SPI port for communication?

Amit Ashara said:

Forum inputs

Yes Sir - cb1 reports as ordered.   (Maybe)

We've done the following years ago (shared single static RAM) - pre ARM - between 2 MCUs (8051 class) with success.  Key here was the use of a "WSI" chip which expanded memory far beyond 64KB cut-off - and enabled (w/the addition of some FPGA "glue") the coordinated switch between each MCU and single memory bank.

Memories which require more active & regular "servicing" would appear to challenge - perhaps "over-challenge."

Would not memory vendors be a superior, "investigative tactic/destination?"   (I'd think so)

Besides checking for multi port memories another option to consider might be FIFOs.

Robert

Hello cb1

But not without a glue logic?

Regards
Amit

Amit Ashara said:

Hello cb1

But not without a glue logic?

Regards
Amit

Thank you all for your answers.

Would a Dual Port SDRAM memory do the job?

If so, would you recommend any specific compatible device?

Vendor here is responsible for (just) one of your TWO MCUs - (some) effort is required by the end user... (or you need to torment the DSP MCU forum - too...)

Hello PAk,

We have never experimented with a Dual port SDRAM for the simplest reason that a use case like this is not comprehended. Normally, we would prefer to have a dedicated memory (at slightly higher cost) than complicate a system design

Regards
Amit

It might do the job. The job isn't clear enough to hazard a guess.

For memory expansion, as Amit says, you are probably better off with separate memory.
For high speed communication I'd look at FIFOs

Both of these avoid synchronization issues between processors that you must deal with when using multi port memory. I've not used multi port memory but one method of using it is to set up areas where only one of the processors can write, all processors can read.

If you do go down the dual port route budget at least several days to verify the timing diagrams before designing.

Robert

Robert Adsett72 said:

For memory expansion, as Amit says, you are probably better off with separate memory.
For high speed communication I'd look at FIFOs

Would you recommend a FIFO for this? How deep could it be?

Robert Adsett72 said:

If you do go down the dual port route budget at least several days to verify the timing diagrams before designing.

I thought in a Dual Port, every port had its own timing.

Amit Ashara said:

Normally, we would prefer to have a dedicated memory (at slightly higher cost) than complicate a system design

The question is not have more memory in both MCUs, but to share one. There is no point for us in double a memory setup.

cb1- said:

Vendor here is responsible for (just) one of your TWO MCUs - (some) effort is required by the end user... (or you need to torment the DSP MCU forum - too...)

Yes, and some time ago they released the, now aged M3+DSP Concerto family. Now there is not a solution with an ARM M4 and a fast DSP.

That's a shame.

Will try to ask in the C2000 forum as well...but you know, Amit is my favourite!!

I don't know what this is. However if you're curious about FIFOs then check Digikey or mouser, the small ones are quite inexpensive and multi vendor, not so for the large ones. Needed size is determinable from your burst length and maximum period between reads.

Yes, there are two ports but you need to spend time considering min/ max/ margins, also what happens to the timing when multiple processors access the same chip/ line/ located at the same time. Are their variable mandatory wait states in some circumstances? Are aborts possible?

Remember too there are multiple vendors at least one has a multicore device with Cortex A and multiple DSP cores on the same chip.

Robert

Hello PAk,

It may still be a low memory size dual memory

Regards
Amit

Robert Adsett72 said:

Yes, there are two ports but you need to spend time considering min/ max/ margins, also what happens to the timing when multiple processors access the same chip/ line/ located at the same time. Are their variable mandatory wait states in some circumstances? Are aborts possible?

Maybe a GPIO port could be used as an Enable/Master indication.

Robert Adsett72 said:

Remember too there are multiple vendors at least one has a multicore device with Cortex A and multiple DSP cores on the same chip.

Yes, but many of them are not floating point on the DSP side and not so energy efficient

Amit Ashara said:

Hello PAk,

It may still be a low memory size dual memory

Regards
Amit

As Robert suggested, I have seen many solutions of external shared memories, where only one of the processors can write, all processors can read. That is not the same.

What do you consider low power? The figures I saw were < 2W with dual floating point DSPs and a Cortex A4

Robert