Am I right that HalCoGen enables SDRAM and follow the timing instructions, as HalCoGen does that automatically? I did not see any appropriate tab. I figured HalCoGen would list this setting underneath the main RM48L952ZWT tab.
1.10.2 Enable the SDRAM by writing 0x00004721 to SDRAM Configuration Register (SDCR) 0xFCFFE808. This sets the SDRAM interface to normal mode, 16 bit data bus, CAS latency of 3, four internal SDRAM banks, nine column address bits. Writing this registers causes an automatic initialization of the SDRAM, and it should not be written to or read from for at least 200 micro-seconds.
I saw a reference to DOUT and DIN in the ECLK sub-tab underneath the main RM48L952ZWT tab, however I am not sure that is the right area. Is that where I would make these configuration changes, and if not where?
1.10.3 Enable the discrete input strobe (EMIF_nCS2 which goes to external signal nDSINENA) by writing 0x889244AC to 0xFCFFE810.
1.10.4 Enable the discrete output strobe (EMIF_nCS3 which goes to external signal nDSOUTENA) by writing 0x889244AC to 0xFCFFE814.
