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Glitches on ADC

Peter Johansen
Intellectual 935 points

Other Parts Discussed in Thread: TM4C129ENCPDT

At the Ain2 A/D input, noise spikes are observed at fixed DC input. The device is TM4C129ENCPDT silicon rev 3. See this recording:

When zooming it looks like this:

The input is a resistive voltage division from the separate power supply (3.3V) for the analog GNDA and VREF+/VDDA. The input is filteret by a 100nF capacitor to GNDA and all components are placed few mm from the device pins. VREFA+ and VDDA pins are tied together. The actual test is for full speed 2 MSPS, but the same result shows for 500 KSPS. I have tried 64 clock Sample/hold but it does not affect these pictures. The errata tells about spikes at the Ain0, but not at the other inputs. The PCB is well designed using 4 layers. The processor is running RTOS and Ethernet traffic at the same time. Configuration is 'ADC_TRIGGER_ALWAYS'.

Any ideas if this is an expected behavior or how to make better performance in terms of noise ?

  • 0 in reply to Peter Johansen
    Guru 27665 points
    Another thought Peter, what clock source are you using for the A/D?

    Robert
  • 0 in reply to Genatco
    Intellectual 935 points
    We will check some more power supply details within the next few days.
  • 0 in reply to Peter Johansen
    Intellectual 935 points
    As feedback to all of your good suggestions:

    The clock is set up :
    //
    // Set the clock for both ADCs (ADC0_BASE sets the clock for both ADCs)
    // ADC_CLOCK_DIVIDER == 30 -> set the ADC clock to 16MHz corresponding to 1Msp/s
    // ADC_CLOCK_DIVIDER == 15 -> set the ADC clock to 32MHz corresponding to 2Msp/s
    //
    ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, ADC_CLOCK_DIVIDER);

    For the power supply, we have tried to add more caps, better GND's etc. We could expect to see the periodic digital consumption from DRAM refresh and RTOS running, but the spikes seems random. Maybe minor improvement on the overall results. The spikes are still +/-12 in absolute numbers for the ADC1 and +6/-10 for ADC0.

    I have checked the programming of the sample/hold by looking into the ADCSSTSH0 register for a 64 clocks test. Programming was ok, but no improvement for the results.

    It is interesting to notice, that the spikes are all just for one conversion. Never 2 conversions in a row.

    Unless something really new comes up, we will stop further investigations.
  • 0 in reply to Peter Johansen
    Guru 26105 points

    Hi,

    One last suggestion: try to apply your analog signal between the pin input and the GNDA pin directly, avoiding digital ground return line, since this is inherently noisy. GNDA pin is soldered to GND in a single connection.

    This is recommended  by all brands making cnversion products (AD for example).

  • 0 in reply to Petrei
    Intellectual 935 points
    Agree - already inplemented.
  • 0 in reply to Peter Johansen
    Guru 27665 points
    Peter, have you tried using the internal oscillator instead? It's not unusual for oscillators connected to the digital domain to introduce extra noise, since the internal oscillator is uncorrelated to the digital switching it may help.

    Robert
  • 0 in reply to Peter Johansen
    Guru 56308 points

    >I have checked the programming of the sample/hold by looking into the ADCSSTSH0 register for a 64 clocks test. Programming was ok, but no improvement for the results.

    Data sheet review reveal SSTSH0 register has 32 bit positions, one Nsh for each sample, 8 total FIFO-0. If using 1 sequencer step then HWREG sets REG28 (0x5c) seemingly requires only THS0 be configured.

    We had random bus faults, odd sample noise leaving unused bits REG28 default (Nsh=4). Setting THSn for any programmed sequencer steps (4 samples), HWREG (0x64=0x8888) stopped noise/faults. Considering after seeing this post setting all 8 samples (THSn) HWREG=(0x88888888) even though only 4 samples steps are configured.

  • 0 in reply to Genatco
    Intellectual 935 points
    Actually we have set the ADCSSTSH0 = 0x88888888. We use an 8 step sequence. Isn't that correct ?
  • 0 in reply to Peter Johansen
    Guru 56308 points

    Sure if all 8 steps are configured that makes sense. Would not the series channel resistance at 64x hold times seemingly produce a very high input impedance. Have past calculated for 2MSPS roughly 3.5k ohms up to the ADC mux when Nsh=16 or 0x22222222 0x44444444. Plausible Nsh=64 might be to much hold time driving low density precision versus a desire for higher density and accuracy. 

    Just changed SSTSH0 from having set at 64 totally forgetting channel impedance is relative. Reduced Nsh=8 @1MSPS, 3.5k max channel impedance with 4x HWA @250KSPS. Had planned to kick ADC0/1 clock up to 32Mhz 2MSPS after all samples produced stable data at the lower speed with oversampling.

  • 0 in reply to Peter Johansen
    Guru 56308 points
    Hi Peter,

    Happen to be messing around with an ADC FIFO sample array reviewing difference between C+ static and volatile definitions. The static unsigned short array[x] had much less noise spikes in the filtered data than a non static uint16_t array[x] .

    The data in the static sample FIFO array is kept nonvolatile during repeated calls to the interrupt handler. For some reason spikes were present in the non static array filter data that dissipate entirely when array was again declared static. The odd thing is the conditional tests that fill the array with FIFO data monitors several ADC channels in a scanning method to match the constrained sequencer steps.