please tell me where the ram parity stored at?

Which part and which RAM (main, MibADC, DCAN, Flexray, ..) are you asking about?

Dear Bob
I am working on "6.3.2 Support for Cortex-R4F CPU's Address and Control Bus Parity Checking" and its selftest routine, so I was asking about the main ram, where is the parity bits stored, I'd like to view them via debugger memory viewer.
Leo

Dear Bob
I happen to be looking at dma parity check now.
I understand that after entering test mode parity bits are mapped to the control packet RAM starting address A00h.
So my question is before entering test mode, where are the parity bits? Can I view them through debugger?
Leo

Dear Bob
I find another strange thing, it says that "there is one parity bit for 16 bits of the ADC RAM." in SPNU515B page 948.
Actually I find that, the bit15 is the parity bit for bit0-14,
I enabled writing to adc ram
then I do (*(volatile uint32 *)0xFF3E0000U) = 0U; then I saw 1000000000000000 (binary) at that 0xFF3E0000U
if i do (*(volatile uint32 *)0xFF3E0000U) = 1U; then I saw 0000000000000001 (binary)
so for each 16bits in adc ram, 15bits are for data, the last bit is the parity bit of the first fifteen bits.
If I am correct about this speculation, the user guide will wrong. Am I right？
Leo

Sorry, too much questions. But I cannot stop asking.
"The ADC RAM address which generated the parity error is captured for host system debugging, " SPNU515B page 948.
but I find that ADPARADDR Register keeps 0 in my parity selftest routine.
then I saw "In emulation mode, this address is maintained frozen even when read"
Is emulation mode as same as selftest mode?
Leo