Dear All
According to my understanding, there is a comparator, and there are always two inputs into it. And the inputs will be compared, if mismatch. CPU may think something is wrong,here are my questions.
1.what are the two inputs, what were compared exactly?
2.if mismatch, any interrupt will be generated, esm channel will be signalled?
3 what Redundant Address Decode protects on earth?
Regards
Leo
Hi Leo,
I don't know which device you use. We have slightly different SRAM controller for different architectures. But the redundant address decode logic is pretty much the same regardless of which SRAM controller. Below is a diagram to illustrate the redundant decode. The address coming from the bus master (i.e. CPU or DMA) passes through two different address decoders. The decoder's job is to decode the incoming address and generate the chip select to the intended memory bank which stores the data the bus master wants to retrieve. The outputs of the two decoders are compared to each other. Basically this is what the redundant address decode does. There is nothing you need to do from a user stand point. You don't encode/decode anything as a programmer.
