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RM48 SDRAM Layout Considerations

F2
Prodigy 735 points
Other Parts Discussed in Thread: RM48L952

Hi Team,

We're currently working on a RM48L952 layout and have a couple questions related to the SDRAM:

1. What trace impedance should be used for Address and Databus lines?

2. If length matching should be applied to Address and Databus, what tolerance on length matching should be followed?

Thanks!

Fabio

  • 0
    TI__Guru 68920 points
    Fabio,

    Regarding the trace impedance - likely that will be driven by the PCB and you'll need to terminate correctly for the impedance of the traces.
    The IBIS models for the device can be used to analyze this.

    For the length - the SDRAM should be placed close to the MCU and the CLK pin to the SDRAM should be oriented so that it is shortest.
    I wouldn't worry about length matching for SDRAM but rather just minimizing the trace lengths to avoid signal integrity problems.

    You should at very least source terminate the CLK line and if possible most of the other signals starting w. the longer ones.
    There will probably be some signals that need 2" to 3" to route..

    -Anthony