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ESM error pin activated when enabling group1 influence

Martin Beaucage
Intellectual 860 points
Other Parts Discussed in Thread: TMS570LC4357

Hello,

We are using processor TMS570LC4357 on a custom board. While working on implementing the external watchdog and reset on error pin activation, I got the following problem.

I configured the ESM module to generate High level FIQ interrupt for all 3 groups. I know this part works because I observed that when I read a flash address that was not written, I get an ECC error and the ESM interrupt is called.

The problem I have is when I enable the group1 influence on the error pin, the pin immediately gets pulled down and there is no error channels reported and no interrupt generated. I enable the influence by doing:

esmEEPAPR1 = 0xFFFFFFFFUL;

esmIEPSR4  = 0xFFFFFFFFUL;

esmIEPSR7  = 0xFFFFFFFFUL;

The error pin gets activated but the state registers are all 0 and no interrupt is generated.

esmSR1 = 0x0

esmSR2 = 0x0

esmSR3 = 0x0

esmSR4 = 0x0

esmSR7 = 0x0

Have you ever seen this condition?

By playing around with the enable bits, I found that if I leave bit 52 to 0 the problem doesn’t occur:

regEsm.esmEEPAPR1 = 0xFFFFFFFFUL;

regEsm.esmIEPSR4  = 0xFFEFFFFFUL;

regEsm.esmIEPSR7  = 0xFFFFFFFFUL;

From this I assume there is a “CPU Interconnect Subsystem - Global error” error but I can’t find a cause for this.

Do you have an idea?

Thanks,

Martin

  • 0
    TI__Guru 72500 points

    It looks like you have run into the issue referred to as DEVICE#48. Here is the description from the errata document:

    The errata documents are SPNZ180 (for rev A silicon) or SPNZ232 (for rev B silicon).

  • 0 in reply to Bob Crosby
    Intellectual 860 points

    Hello Bob,

    I have seen this errata, so I investigated the STC module.

    Right now we don't do STC test, we don't enable the self test. Also I checked the testFail bit in register STCGSTAT of STC1 and 2 and both bit are 0. From this I assumed this was not the problem.

    Also if this was the problem, shouldn't EMS register ESMSR4 show 0x00100000? in my case it is 0.

    Thanks,

    Martin

  • 0 in reply to Martin Beaucage
    TI__Guru 72500 points
    Martin,

    It looks like that ESM flag can be set by any CPU reset (other than nPORRST). Are you doing either a CPU reset, software reset or nRST? Are you running GCLK at 300MHz? Did you check the ESM flag bit before enabling the ESM to generate NMI?
  • 0 in reply to Bob Crosby
    Intellectual 860 points

    Hello Bob,

    The problem occurs when we turn ON the board. The CPU power and nPORESET pin is managed by TI power supply TPS65381. Pin nRST is always high (not used). When we activate the group1 influence on error pin, the pin gets driven low and the power supply chip makes a nPORESET again. When we activate the group1 influence on error pin a second time the pin doesn't get driven low. It does it only 1 time when we turn ON the board, this is why it took me some time to notice this problem.

    Our clock configuration puts GCLK at 300MHz, HCLK at 100MHz and all other clocks (avClkx, vClkx, rtiClk) at 100MHz.

    I checked the ESM flags before enabling the group1 influence on the error pin and after. The error pin is high before and low after. But I enable the NMI only after enabling the group1 influence so I thought this was why I was not getting an interrupt. But when I enable the NMI before the influence of group1 it doesn't change anything. The error pin still gets driven, no error cause is reported and no interrupt is generated.

    Martin