TM4C129ENCPDT Watchdog using LFIOSC

Hi Barry,

LFIOSC is intended for use during deep-sleep power saving mode. The ALTCLK field of ALTCLKCFG register is used to select clock source for watchdog. The applciation should not modify the ALTCLK field while the watchdog is enabled and running.

Regards,
QJ

Thanks for the response QJ

From further reading I found that watchdog 0 uses the system clock and watchdog 1 uses the AltClock

However when I add a watchdog 1 definition to my hardware file (TM4C129ENCPDT definitely has bath watchdog 0 and 1) I get a hardware exception when I call Watchdog_Open for watchdog 1.  Below is my watchdog object initialisation (Not sure if I have the correct interrupt number for watchdog 1, couldn't find any examples and hw_int doesn't have any interrupt marked as watchdog 1)

// Watchdog configuration structure
const WatchdogTiva_HWAttrs watchdogTivaHWAttrs[A30307P26_WATCHDOGCOUNT] = {
    // A30307P26_WATCHDOG0 with 1 sec period at default CPU clock freq (120MHz)
    {WATCHDOG0_BASE, INT_WATCHDOG, (~0), 80000000},
    {WATCHDOG1_BASE, INT_WATCHDOG, (~0), 32000},
};

const Watchdog_Config Watchdog_config[] = {
    {&WatchdogTiva_fxnTable, &watchdogTivaObjects[0], &watchdogTivaHWAttrs[0]},
    {&WatchdogTiva_fxnTable, &watchdogTivaObjects[1], &watchdogTivaHWAttrs[1]},
    {NULL, NULL, NULL},
};

I also note in the WatchdogTiva.c file there doesn't seem to be any polling of the WRC bit in WDTCTL which the hardware manual for the processor says MUST be done for watchdog1.

Is this a case of the API not supporting watchdog 1?

Regards

Barry

Hello Barry,

Did you check when an access to the WDT1 is done, the RCGCWD in System control module is set to 1 for the corresponding watchdog. The WDT1 bit position is 1 in the RCGCWD register. So if both watchdogs are enabled then the value should be 0x3 before an access is made to the register.

Regards
Amit