According to technical manual, no SCI configurations shall be made while SWnRST bit is active. What this "configuration" exactly means, all SCI registers, some specific registers? It is not specified anywhere. It cannot be all SCI registers because at least interrupts etc. must be able to set during run, but RX enable is in same register as that SWnRST bit.
Is this really true? This would yield to a situation while you cannot for example disable RX side while sending data and if such feature is needed a lot of kludge is needed in application sw...
HALCoGen sciSetBaudrate() function does not disable SWnRST, is this a bug, I think so?
sciSetBaudrate() function also calculates baudrate wrongly even though it has been once fixed (see e2e.ti.com/.../390756)
It should round the result not cut. For example VLCK 110MHz and trying to get 115200 speed (exact factor is 58,6788), HALCoGen init code sets it to 59 (which is best value if using only P) but if calling sciSetBaudrate(115200) it sets the value to 58 which is not optimal when not using M. This rounding error makes higher bauds to go out of tolerated range faster.
sciSetBaudrate() does not set M bit either if SCI/LIN interface and asyncronous mode, why? With higher speeds P term is not enough unless VCLK magically match to requested baudrate.
My Halcogen code versions for sci.c are
* @date 02-Mar-2016
* @version 04.05.02