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SCI: SWnRST bit, not possible to disable RX while sending data?

Other Parts Discussed in Thread: HALCOGEN

According to technical manual, no SCI configurations shall be made while SWnRST bit is active. What this "configuration" exactly means, all SCI registers, some specific registers? It is not specified anywhere. It cannot be all SCI registers because at least interrupts etc. must be able to set during run, but RX enable is in same register as that SWnRST bit.


Is this really true? This would yield to a situation while you cannot for example disable RX side while sending data and if such feature is needed a lot of kludge is needed in application sw...


HALCoGen sciSetBaudrate() function does not disable SWnRST, is this a bug, I think so?

sciSetBaudrate() function also calculates baudrate wrongly even though it has been once fixed (see e2e.ti.com/.../390756)

It should round the result not cut. For example VLCK 110MHz and trying to get 115200 speed (exact factor is 58,6788), HALCoGen init code sets it to 59 (which is best value if using only P) but if calling sciSetBaudrate(115200) it sets the value to 58 which is not optimal when not using M. This rounding error makes higher bauds to go out of tolerated range faster.

sciSetBaudrate() does not set M bit either if SCI/LIN interface and asyncronous mode, why? With higher speeds P term is not enough unless VCLK magically match to requested baudrate.

My Halcogen code versions for sci.c are
*   @date 02-Mar-2016
*   @version 04.05.02

  • Jarkko,

    Thanks for pointing this out. Vague wording like this is one of my pet peeves.

    The best answer I can give you right now is that I would not equate configuration with 'register writes' so that like you said it cannot be all SCI registers.

    There is a section in the TRM: For example in SPNU499b - 26.5 SCI Configurations that lists the fields that are configured between SWnRST=0 (step 2) and SWnRST=1 (second to last step). Without any other information this is what i'd go by. But I'll enter a ticket on the TRM asking for clarification.

    I get a bad link from: e2e.ti.com/.../390756 above. Maybe you can send me your HalCoGen project? It may be something that is specific to the device you are using in case something got missed. Though it sounds like a different computation method is being used between the GUI and the software. If you send me the files you are looking at including the generated one I'll check.

    But it does appear that baudrate is in the config list in setion 26.5 so I think that needs a ticket on it.

    Thanks and Best Regards,
    Anthony
  • Jarkko,

    Would you pls check something as well -- in sciSetBaudrate this line:

    temp2 = ((vclk)/((float64)temp))-1U;

    Could be changed to:

    temp2 = ((vclk)/((float64)temp))-0.5;

    That's equivalent to adding 0.5 before the cast to integer:
    sci->BRS = (uint32)((uint32)temp2 & 0x00FFFFFFU);

    I believe the cast should just 'truncate' instead of round and if you're low by 1 bit I think adding 0.5
    before the cast would mean rounding and would give you a closer result especially when the divider is < 100.

    -Anthony
  • This is code from the GUI - note the use of Math.round

     <!-- SCILIN FORMAT -->

     <script>

       function calcSciPrescale2()

       {

         var vclk     = getValueDouble("SYSTEM", "CLKT_VCLK1_FREQ") * 1000000

         var baud     = getValueDouble("SCI2", "SCILIN_BAUDRATE")

         var prescale = Math.min(Math.max(0, Math.round(vclk /(baud * 16) - 1)), 16777215)

         var actual   = prescale == 0 ? (vclk/32) : (vclk/(16*(prescale+1)))

         setValue("SCI2", "SCILIN_PRESCALE", prescale)

         setValue("SCI2", "SCILIN_ACTUALBAUDRATE", actual.toFixed(0))

       }

     </script>

    Googled that in Javascript and hit here:   

    So I think rounding is whats missing. 

    If you add 0.5 and truncate that should be the same as rounding, assuming the number is positive which it has to be in this case..

    So I think changing the formula as in the previous post shoudl give you results that match the GUI.  I'll file a ticket on this though as well as on not using SWnRST.     Although for the latter I could see an alternative being that you are required to assert SWnRST before calling the function being added to the documentation.   Not sure which would be the least disruptive result to be honest.

  • Tickets:

    TRM to define which bits are configuration: SDOCM00122318
    HalCoGen - sciSetBaudrate() does not follow SWnRST=0 requirement SDOCM00122319
    HalCoGen - sciSetBaudrate() does not round result to nearest integer: SDOCM00122320
  • Yes, using -0.5 instead of -1.0 solves the problem (and that is 'rounding' (to nearest integer) even though the end result is still truncated :)). I'll think that I do not need to send any code anymore because this trivial to reproduce with 110MHz & 115200 setting and you already found conflict between init code and function.

    However, if using M term then the P needs to be truncated like originally and calculate M on top of it (and if rounding the M goes > 15 then, M=0 and P += 1).


    For SWnRST bit in sciSetBaudrate() function I would make an argument for function where caller can decide whether the bit is toggled or not. Worst way to solve the issue is to put remark with white font into some manual, decent way would be to add remark to function header :). One 100% preventing misuse but maybe annoying solution would be to enter while(1) loop if bit is not in proper position.

    Anyway the caller should have an control what is the bit state after exiting the function to prevent the situation where SCI starts running "accidentally" (similar issue is also with init code, it is impossible with this init function to configure RX DMA active to that DMA is running when SCI is started to 100% prevent overflow (sciInit() clears CLEARINT while RX_DMA's bits should be active but HALCoGen does not offer interface to put those on in SETINT and there is no "usercode areas" between SET/CLEARTINT and SWnRST enable). Of course you can modify existing function but when generating new HALCoGen code your changes will be always overwritten resulting in an situation where at some point you accidentally overwrite your changes and generate nasty bug to sw.