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How to determine stack/RAM usage

Sarah Weinberger
Expert 1915 points
Other Parts Discussed in Thread: UNIFLASH, HALCOGEN, RM57L843

Chip: RM48L952ZWT

Environment: Halcogen, CCS (Code Composer Studio), UniFlash, TI compiler

Memory: 16MB SDRAM plus internal to the chip; stack uses internal, while heap uses the external

How can I determine how much of the stack and memory I am using and if I am getting close to filling or exceeding one of the sections?

MEMORY
{
    VECTORS (X)  : origin=0x00000000 length=0x00000020
    FLASH0  (RX) : origin=0x00000020 length=0x0017FFE0
    FLASH1  (RX) : origin=0x00180000 length=0x00180000
    STACKS  (RW) : origin=0x08000000 length=0x0003fe00
    RAM     (RW) : origin=0x0803fe00 length=0x00000200

/* USER CODE BEGIN (2) */
    RAM2    (RW) : origin=0x80000000 length=0x01000000
/* USER CODE END */
}

SECTIONS
{
    .intvecs : {} > VECTORS
    .text    : {} > FLASH0 | FLASH1
    .const   : {} > FLASH0 | FLASH1
    .cinit   : {} > FLASH0 | FLASH1
    .pinit   : {} > FLASH0 | FLASH1
    .bss     : {} > RAM2
    .data    : {} > RAM2
    .sysmem  : {} > RAM2

    FEE_TEXT_SECTION : {} > FLASH0 | FLASH1
    FEE_CONST_SECTION : {} > FLASH0 | FLASH1
    FEE_DATA_SECTION : {} > RAM2
#endif
/* USER CODE END */
}

 

  • 0 in reply to Anthony F. Seely
    Expert 1915 points
    Hi Anthony, thank you for answering my questions on a Sunday.

    I finally read all your responses in detail, however I still do not understand the connection with setting the SDRCR register and the cause of my SDRAM not working, which is the enabling of the discrete signals using the code that I gave earlier. I can copy again, if you want. I had to comment out the discrete IO initialization code for the SDRAM to start working.

    I can and will make the change requested, but

    1. Will these changes enable me to enable discrete IO and still be able to use SDRAM?

    2. The change you requested means NOT using the user code sections. That will cause issues when generating code.

    3. Aside from the 2 SDRCR (one really, as the second instance already has 157), do I need to make any other changes?
  • 0 in reply to Sarah Weinberger
    TI__Guru 68920 points

    Hi Sarah,

    Sarah Weinberger said:
    1. Will these changes enable me to enable discrete IO and still be able to use SDRAM?

    I doubt that making this change alone will solve the issue you are having,  but it will make sure that the initialization of the SDRAM is within the SDRAM spec. So I would strongly recommend making the change anyway - as it reduces the 'chaos' if you will.  If we don't know for sure that the SDRAM is initialized correctly - it could make figuring out the next issue with discrete IO that much more difficult.

    Sarah Weinberger said:
    2. The change you requested means NOT using the user code sections. That will cause issues when generating code.

    You can actually put the change in user code like this and it may be better to do so than to modify the template actually.   The template is just useful because you can see what calculations are performed whereas the code emitted just has hard-coded constants. 

    void emif_SDRAMInit(void)
{
/* USER CODE BEGIN (2) */
   uint32 buffer;

   emifREG->SDTIMR  = (uint32)((uint32)0U << 27U)|
                      (uint32)((uint32)0U << 24U)|
                      (uint32)((uint32)0U << 23U)|
                      (uint32)((uint32)0U << 20U)|
                      (uint32)((uint32)0U << 19U)|
                      (uint32)((uint32)0U << 16U)|
                      (uint32)((uint32)0U << 12U)|
                      (uint32)((uint32)0U << 8U)|
                      (uint32)((uint32)0U << 7U)|
                      (uint32)((uint32)0U << 4U)|
                      (uint32)((uint32)0U << 3U);

 /* configure refresh rate*/
   emifREG->SDSRETR = (uint32)0U;
   emifREG->SDRCR   = 2000U;

/**  -general clearing of register
*    -for NM for setting 16 bit data bus
*    -cas latency
*    -BIT11_9CLOCK to allow the cl field to be written
*    -selecting the banks
*    -setting the pagesize
*/   
    emifREG->SDCR   = (uint32)((uint32)0U << 31U)|                               	
                      (uint32)((uint32)1U << 14U)|                               	
                      (uint32)((uint32)2U << 9U)|  	
                      (uint32)((uint32)1U << 8U)|                                	
                      (uint32)((uint32)2U << 4U)|              	
                      (uint32)((uint32)elements_256);         	
/* wait for a read to happen*/
   buffer           = *PTR;                                	
   buffer           = buffer;
   emifREG->SDRCR   = 157U;

#if 0
/* USER CODE END */

   uint32 buffer;

   emifREG->SDTIMR  = (uint32)((uint32)0U << 27U)|
                      (uint32)((uint32)0U << 24U)|
                      (uint32)((uint32)0U << 23U)|
                      (uint32)((uint32)0U << 20U)|
                      (uint32)((uint32)0U << 19U)|
                      (uint32)((uint32)0U << 16U)|
                      (uint32)((uint32)0U << 12U)|
                      (uint32)((uint32)0U << 8U)|
                      (uint32)((uint32)0U << 7U)|
                      (uint32)((uint32)0U << 4U)|
                      (uint32)((uint32)0U << 3U);

 /* configure refresh rate*/
   emifREG->SDSRETR = (uint32)0U;
   emifREG->SDRCR   = 250U;

/**  -general clearing of register
*    -for NM for setting 16 bit data bus
*    -cas latency
*    -BIT11_9CLOCK to allow the cl field to be written
*    -selecting the banks
*    -setting the pagesize
*/   
    emifREG->SDCR   = (uint32)((uint32)0U << 31U)|                               	
                      (uint32)((uint32)1U << 14U)|                               	
                      (uint32)((uint32)2U << 9U)|  	
                      (uint32)((uint32)1U << 8U)|                                	
                      (uint32)((uint32)2U << 4U)|              	
                      (uint32)((uint32)elements_256);         	
/* wait for a read to happen*/
   buffer           = *PTR;                                	
   buffer           = buffer;
   emifREG->SDRCR   = 156U;

/* USER CODE BEGIN (3) */
#endif
/* USER CODE END */
}

    Sarah Weinberger said:
    3. Aside from the 2 SDRCR (one really, as the second instance already has 157), do I need to make any other changes?

    Not really - the code above is my idea of what yours should eventually look like although you may want to copy/paste your code for 10MHz like i did, putting a second copy into the /* USER CODE */ section and putting the #if 0 / #endif around the generated code.    Then change the first SDRCR to 2000.

    This isn't 'great' because any changes in the GUI to the SDRAM timings would need to be copied from the #if 0 / #endif generate block back to the user code block but at least it will survive the generation process and any HalCoGen upgrades between now and when we fix the function properly.