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TM4C1294NCPDTi3:
Configuring dead band inversion pwmB drive and not rolling that same protection at some point to pwmA creates an inefficient 1/2 bridge scheme.
That is to say one side of 1/2 bridge, typically the low side has a much longer On time due to pwmB inversion period being longer during dead band than non-inversion pwmA On times. The dead band FALL(FED) inverted pwmB On time is not of the same pulse width as pwmA RISE (RED) non-invert state. That assumes all FETS are N channel and require active High to turn them on.
Calls to PWMDeadBandDisable() should decouple CMPB yet don't decouple dead band generators pwmB from PWM0 or make pwmB inverted from pwmA state as expected. The same case exists in Stellarisware using the exact same syntax as Tivaware, assumed decoupling dead band was successful when all that occurs is pwmB signal inversion when enabled.
If we program PWMnDBRISE/FALL registers 0x0 and then clear PWMnDBCTRL Enable bit, the pwmB output reverts back to non-inverted state and PWM0/1 pass through dead band untouched. Otherwise PWMnDBRISE/FALL original configure values set in PWMDeadBandEnable() remains in effect and assert even when DBCTRL enable is clear.
So it seem we can not decouple PWM0/1 from dead band simply by clearing PWMnDBCTRL enable bit as PWMDeadBandDisable() asserts to clear enable.
Why?
If PWMDeadBandDisable() could clear pwmB inverted state it might some how be possible to invert both pwmA and pwmB in equal dead band wrappers every other cycle of RED/FED. That way the same active pulse width length can exist pwmA or pwmB at opposite time intervals.
From our view point this must be clarified by TI engineers in order the model in datasheet has any meaning to this find. Perhaps some undocumented Anomaly exist?
The good news is the TM4C1294 pwmB dead band RED pulse width is not truncated when PWMnDBENABLE bit is set inverse as described above. LM3S8971 software migration to TM4C1294 produced the same issue. Truncated pwmB RED pulses occur when the DBENABLE bit is disabled during the dead band enabling call PWMEnableDeadBand() in opposition to the intent of enabling dead band.
Patch below seems to clear dead band, decouple PWM0/1 from pwmA/B dead band generators both LM3S8971 and TM4C1294. The inverse with disable after setting PWMnDBFALL/RISE registers seems to latch the banding mode 6 thus inserting RED/FED delays into the pulse width pwmA as intended pwmB not so much. The original Tiva enable dead band mode did not produce any change to RED/FED delays as expected. Oddly RED/RED register values seem to be a smaller multiple of PWM clocks than calculated. Clearing RED/FED dead band registers 0x0 before setting new and latched values did not seem to help.
6-21-2016: The RED/FED delays are appearing on opposite co-phase 1/2 bridge partners in cycles. Mentioned above saw no change (FED/RED) same 1/2 bridge simply remained static roughly 200ns when the delay registers explicitly set to a new values and re-tested. The diagrams do not show a cycle scheme (RED/FED) co phase pairs as being the real time event (High to Low co-phase). The RED/FED delays are drawn statically each generator with out any mention of 1/2 bridge crossing behavior being indicated in the table. That explains dead band is not being fully elaborated in the data sheet text and scope captures in real time events are in opposition to the simple Figure 3-10.
PWMClearDeadBand(void)
{
unsigned short usDeadTimePwmA = 0;
unsigned short usDeadTimePwmB = 0;
// Clear the dead band PWMnDBRIS/FALL registers.
HWREG(PWM0_BASE + PWM_GEN_1 + PWM_O_X_DBRISE) = usDeadTimePwmA;
HWREG(PWM0_BASE + PWM_GEN_1 + PWM_O_X_DBFALL) = usDeadTimePwmB;
HWREG(PWM0_BASE + PWM_GEN_1 + PWM_O_X_DBCTL) = PWM_X_DBCTL_ENABLE;
HWREG(PWM0_BASE + PWM_GEN_2 + PWM_O_X_DBRISE) = usDeadTimePwmA;
HWREG(PWM0_BASE + PWM_GEN_2 + PWM_O_X_DBFALL) = usDeadTimePwmB;
HWREG(PWM0_BASE + PWM_GEN_2 + PWM_O_X_DBCTL) = PWM_X_DBCTL_ENABLE;
HWREG(PWM0_BASE + PWM_GEN_3 + PWM_O_X_DBRISE) = usDeadTimePwmA;
HWREG(PWM0_BASE + PWM_GEN_3 + PWM_O_X_DBFALL) = usDeadTimePwmB;
HWREG(PWM0_BASE + PWM_GEN_3 + PWM_O_X_DBCTL) = PWM_X_DBCTL_ENABLE;
}
