Just found an error inside the HalCoGen (4.05.02) code that calculates the value of the SDRCR register. It may be an issue in earlier versions as well.
This register sets the *maximum* delay between successive refreshes in order to completely refresh the SDRAM within it's specified time.
For example, normally an SDRAM datasheet will specify something like "4096 refresh cycles every 64 ms" ; and HalCoGen will compute the value of the SDRCR to be (64ms / (4096 * emif clock period)). For a 100MHz EMIF 50MHz EMIF clock the result would be 760 cycles, and the EMIF would make sure at least 1 refresh occurs during this time period.
But after computing the value correctly the HalCoGen generator code incorrectly truncates the value to 5-bits (max value of 31) whereas the RR register accepts a maximum value of 8191.
If you are suffering from poor EMIF SDRAM performance and use HalCoGen please check the value you have configured in the SDRCR register. If it is not >> 500 then I would strongly suggest checking for this issue.
To workaround the issue at the moment you would need to place a correct refresh value in the last /* USER CODE BEGIN () */ /* USER CODE END */ location of the file emif.c in the function void emif_SDRAMInit(void).
You want to set:
emifREG->SDRCR = <correct value>;
Where correct value is based on the calculation described above and the SDRAM datasheet requirement of XX refreshes every YY ms.
EDIT:
Note the correction - I recalculated with 50MHz because of the typical SDRAM speed available on Hercules devices.
