TMS570LC4347: runtime jitter

Marc,

Did you checked the size of you application? It might fit in the instruction cache if you compile with Thumb2 (16bit) instructions.

Best Regards,
Christian

Hi Christian,

Cache effect could be a possibility but in a complicated way because the 16 bit code is 370KB while the 32 bit code is 450KB.

Thanks for your answer

Marc

Marc,

You might also want to look into the Performance Monitoring Unit (PMU) which is part of the ARM Cortex-R5F core (described in ARM Cortex-R5F TRM). It enables you to cycle accurate measure execution times and to count events like data/instruction cache misses to better understand performance implications.

Best Regards,
Christian

Going PMU is a hard way.
I'll look at this when time permits.

Thanks for the suggestion.

Marc

Marc,

The PMU is supported by HALCoGen, you could configure the counters in the GUI and you have all the APIs to configure it and to read out the data:

_pmuInit_();
_pmuResetCycleCounter_();
_pmuStartCounters_(pmuCYCLE_COUNTER);

benchmark code

cycles = _pmuGetCycleCount_();
_pmuStopCounters_(pmuCYCLE_COUNTER);

This should make it easy to use, but for sure you have to consult the ARM Cortex-R5 TRM for details on the different counters.

Best Regards,
Christian

Hi all,

Perhaps the following can lead to an explanation: the prefetch depth is enhanced when the code is 16 bits and so the DPU runs smoother. This could be monitored with the event 0 and 16 of the PMU.

Greetings,

Marc