Hello,
We have been running some benchmarks to evaluate the performance of the TMS570LS3137 RevD EMIF.
We ran a Dhrystone benchmark with the code located in the Flash memory, the stack in the RAM memory, and the data/heap in an external SRAM memory (35 ns speed grade).
We have trouble understanding the results we mesured.
The first thing is that we have not been able to make the EMIF working accordingly to the SRAM timings. We modified the EMIF asynchronous configuration to gradually reduce the timings, but it appears that our test fails under a value, which is around the double of our SRAM cycle time. We don't understand why we can't have the EMIF working in such a configuration. Is there some limitation on the interface ?
The second thing is that our results seem very depend on thefrequency of the EMIF VCLK internal clock.
We have measured a given performance while running at 80 MHz. Then, we have increased the EMIF internal frequency at 90 MHz, and we have measured a +50% increase of performance. This is strange, because when analysing the timings on the EMIF interface, the signals sequencing is more or less the same than at 80MHz. More puzzling, we have run a test at 45 MHz, and we obtained a performance slightly better than at 80 MHz...
To sum up :
performance @ 90 MHz >>> performance @ 45 MHz > performance @ 80 MHz.
We have of course checked our test, but everything seems fine. So, we would like to have more details on the behaviour we observed. What are the parameters that can have an impact on the EMIF asynchronous performance ?
Thank you in advance,
Best regards,
PGC
