Hello,
I was configured DMA for SCI transfer in TMS570LS20216. In my program, I want to receive some files from PC and send them back to check each file is received correctly or not.
The receive function works properly but there is a problem in transmit side. The micro can receive all the files coming from the PC but it can’t do more than one transmit. Something like setting the ONESHOT bit which makes a single transfer happen.
Bellow you can see the DMA configuration:
/* setting dma control packets for transmit */
void dmaSciConfigCtrlPacket_TX(uint32 sadd,uint32 dadd,uint32 dsize)
{
/* TX line, DMA configuration for transmission via SCI bus */
dmaReqAssign(DMA_CH0,DMA_REQ_SCI1_TX); /* Assign DMA request to channel 0 */
dmaEnableInterrupt(DMA_CH0, BTC); /* Enable interrupt of block complete */
g_dmaCTRLPKT_TX.SADD = sadd; /* source address */
g_dmaCTRLPKT_TX.DADD = dadd; /* destination address */
g_dmaCTRLPKT_TX.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT_TX.FRCNT = dsize; /* frame count */
g_dmaCTRLPKT_TX.ELCNT = 1; /* element count */
g_dmaCTRLPKT_TX.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT_TX.ELSOFFSET = 0; /* element source offset */
g_dmaCTRLPKT_TX.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_TX.FRSOFFSET = 0; /* frame source offset */
g_dmaCTRLPKT_TX.PORTASGN = 4; /* port b */
g_dmaCTRLPKT_TX.RDSIZE = ACCESS_8_BIT; /* read size */
g_dmaCTRLPKT_TX.WRSIZE = ACCESS_8_BIT; /* write size */
g_dmaCTRLPKT_TX.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT_TX.ADDMODERD = ADDR_INC1; /* Post-incremented read */
g_dmaCTRLPKT_TX.ADDMODEWR = ADDR_FIXED; /* Fixed address write */
g_dmaCTRLPKT_TX.AUTOINIT = AUTOINIT_ON; /* autoinit */
dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT_TX); /* - setting dma control packets for transmit */
}
/* setting dma control packets for receive */
void dmaSciConfigCtrlPacket_RX(uint32 sadd,uint32 dadd,uint32 dsize)
{
/* RX line, DMA request for reception via SCI bus */
dmaReqAssign(DMA_CH1,DMA_REQ_SCI1_RX); /* Assign DMA request to channel 1 */
dmaEnableInterrupt(DMA_CH1, BTC); /* Enable interrupt of block complete */
g_dmaCTRLPKT_RX.SADD = sadd; /* source address */
g_dmaCTRLPKT_RX.DADD = dadd; /* destination address */
g_dmaCTRLPKT_RX.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT_RX.FRCNT = dsize; /* frame count */
g_dmaCTRLPKT_RX.ELCNT = 1; /* element count */
g_dmaCTRLPKT_RX.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT_RX.ELSOFFSET = 0; /* element source offset */
g_dmaCTRLPKT_RX.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_RX.FRSOFFSET = 0; /* frame source offset */
g_dmaCTRLPKT_RX.PORTASGN = 4; /* port b */
g_dmaCTRLPKT_RX.RDSIZE = ACCESS_8_BIT; /* read size */
g_dmaCTRLPKT_RX.WRSIZE = ACCESS_8_BIT; /* write size */
g_dmaCTRLPKT_RX.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT_RX.ADDMODERD = ADDR_FIXED; /* Fixed address read */
g_dmaCTRLPKT_RX.ADDMODEWR = ADDR_INC1; /* Post-incremented write */
g_dmaCTRLPKT_RX.AUTOINIT = AUTOINIT_ON; /* autoinit */
dmaSetCtrlPacket(DMA_CH1,g_dmaCTRLPKT_RX); /* - setting dma control packets for receive */
}
void scidmainit(uint8 direct){
/* Enable DMA now to make sure it's ready to take requests */
dmaEnable();
if (direct == 0){
/* DMA Channel 0 Control Packet Config (Writing to SCITD) */
dmaSciConfigCtrlPacket_TX((uint32)&(txBuff_1), (uint32)((uint8*)&(sciREG->TD)+3) , size);
dmaSetChEnable(DMA_CH0, DMA_HW); /* Trigger DMA transmission */
sciREG->SETINT |= SCI_SET_TX_DMA; /* Enable SCI TX DMA request */
}
else{
/* DMA Channel 1 Control Packet Config (Reading from SCIRD) */
dmaSciConfigCtrlPacket_RX((uint32)((uint8*)&(sciREG->RD)+3), (uint32)&(rxBuff_1) , size);
dmaSetChEnable(DMA_CH1, DMA_HW); /* Trigger DMA reception */
sciREG->SETINT |= SCI_SET_RX_DMA | SCI_SET_RX_DMA_ALL; /* Enable SCI DMA request RM_DMA_ALL + RX_DMA */
}
}
And here is my code:
Thanks in advance,
Ehsani
