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Concurrent Parallel XIP Flash and SRAM Design

Hello Amit,

Two points...

In the schematics for the Flash I noted the P1 connector pin-outs are opposite to the X11 connector on the EK. In other words the odd and even sides are swapped.

In the software example you are using EPI0S0, EPI0S1 etc. while in the schematic it is EPIOS0, EPIOS1 etc.

Regards,

Victor

  • Hello Victor,

    The P1 connector is mounted on the bottom of the board. So from a connection perspective the schematic would be shown as swapped.

    The correct nomenclature is as per software. It was an error during entry in schematic that a numeric "0" became alphabet "O".

    Regards
    Amit