EMIF CS not asserting

Brian Viele94

Other Parts Discussed in Thread: HALCOGEN

We're bringing up some Hercules based platforms, and are attempting to use the EMIF in async mode to access some external UART modules. I created a snippet of code to update chip select configurations, and they seem to be setting properly, but when I read from the CS2 address space, the chip select doesn't toggle. I have updated the mode of the pin to GPIOB4 and toggled it successfully, but cannot get the EMIF to toggle the pin when set as CS2.

We have been digging through the ref manual to see if there is anything else that must be configured, but cannot find anything obvious. I have disabled the cache, the MPU is disabled, and everything else in the system (UART, ADC, RTI, etc.) are working fine with interrupts. Is there something in the co-processor registers or other arch regs we need to setup for this to work?

Here is the output from the test code.

Configuring CS2 [0x60000000-0x63ffffff] with 96MHz base clock
RD (Setup, Access, Hold): 1, 3, 1
WR (Setup, Access, Hold): 1, 3, 1

zee:>read 0xfcffe800
Reading 64 words of data starting at address 0xfcffe800
0xfcffe800 :0x40000205 :0xf0000080 :0x00000620 :0x00000080 :0x00200100 :0x3ffffffd :0x3ffffffd :0x3ffffffd :
0xfcffe820 :0x31214610 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000007 :
0xfcffe840 :0x00000004 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000400 :
0xfcffe860 :0x00000000 :0x00000001 :0xfcfcfcfc :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :
0xfcffe880 :0x00000000 :0x00000000 :0x00002091 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :
0xfcffe8a0 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000003 :0x00000000 :0x00000000 :0x00000000 :
0xfcffe8c0 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :
0xfcffe8e0 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :

zee:>read 0x60000000
Reading 64 words of data starting at address 0x60000000
0x60000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :
0x60000020 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :
0x60000040 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :
0x60000060 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :
0x60000080 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :
0x600000a0 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :
0x600000c0 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :
0x600000e0 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :0x00000000 :

over 9 years ago

0 Anthony F. Seely over 9 years ago

TI__Guru 68920 points

Did you call the EMIF async init function before trying to use the chip select?

0 Anthony F. Seely over 9 years ago in reply to Anthony F. Seely

TI__Guru 68920 points

Also don't disable the MPU.
Instead make sure it is enabled and that you have the permissions set properly for EMIF.
If it's disabled - there is a default memory map that is used and I don't think it matches well w. the TMS570 memory map.

0 Brian Viele94 over 9 years ago in reply to Anthony F. Seely

Prodigy 180 points

We're not using halcogen...but yes, we are initializing the assync settings (Note CS2 is set for 3 wait states for rd/wr)

0 Brian Viele94 over 9 years ago in reply to Anthony F. Seely

Prodigy 180 points

This seems....silly...have assumed the MPU (memory protection unit) disabled, it simply does not generate faults...sounds like you're stating that the default mapping is faulty.

Will add in a default MPU mapping and see if that helps.

0 Anthony F. Seely over 9 years ago in reply to Brian Viele94

TI__Guru 68920 points

So if you look at section 7.1 of the CPU TRM (ARM's document ARMDDI0363E) then there is a default memory map listed there.

It's not too bad for the region from 0x6000 0000 to 0x7FFF FFFF actually.
The space at 0x8000 0000 which is where we map SDRAM defaults to Device, Execute Never which isn't a good match for SDRAM.
That's what I was thinking of as the major incompatability.

So if you're not using SDRAM it shouldn't make a difference but anyway the default's in HalCoGen fit the device so may as well use them.

0 Anthony F. Seely over 9 years ago in reply to Anthony F. Seely

TI__Guru 68920 points

Also then, you should try a simple HalCoGen generated program that enables the EMIF and reads/writes from CS[2].
This should just work.

Then you can start comparing against your own program to see what you may have missed in terms of register settings.

0 Brian Viele94 over 9 years ago in reply to Anthony F. Seely

Prodigy 180 points

Started a simple HALCoGen project, and had the same issue...dug through the pinmux settings and found the magic check box "EMIF Output Enable" and yay! Updated our board init code to to set PINMMR174[9:8] == 0x2 from 0x1 and happiness ensues!

Thanks for the suggestions.

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EMIF CS not asserting