I'm using TMS570LS1227ZWT with silicon revision C.
In its silicon errata (SPNZ218C), SSWFF021#44 was removed compared with silicon revision B.
And PLL lock time in the TRM (SPNU515B, p.395) was changed to
(512 x TOSCIN) + (1024 x NR x TOSCIN) .
Does it mean that the PLL Lock Time above is not the silicon errata but the new specification?
Best Regards,
Satoshi Shinohara
