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Performance difference when enabling ECC for Flash

Hiroshi Kimizuka
Expert 4400 points


When enabling ECC calculation for the on-chip Flash, how much is the performance differentiation(degradation) on TMS470MF ?

If the pipeline mode is activated, can this calculation and other relevant overhead be hidden under the pipeline ?

Thanks and Best Regards,

KIMIZUKA

 

  • 0
    TI__Genius 14205 points

    Hi Kimizuka,

    I have forwarded your questions to the concern Application Engineer.  We will get back to you as soon as possible.

    Cheers!!!
    Prathap

     

     

  • 0
    TI__Guru 59540 points

    Hello Kimizuka,

    When using flash with single error correction double error detection (SECDEC or ECC) enabled, there is no degredation to the performance of the microcontroller. However, keep in mind that the wait states for flash need to be set according to the system operating frequency as follows:

    HCLK <= 28MHz : no programmed data or address wait states required with or without ECC enabled.

    28MHz < HCLK <= 56MHz : 1 programmed data wait state and no address wait states required with or without ECC enabled.

    56MHz < HCLK <= 80MHz: 2 programmed data wait states and no address wait states required with or without ECC enabled.

     For HCLK > 28MHz, pipeline mode must be enabled.

     Please let me know if there are any additional questions.

     

    Regards,

    Chuck Davenport