TMS570LC4357 - Trace

Hi Juergen,
Our Trace expert is currently out of office. I have forwarded your post to him so he can provide more insights later. In the meantime please refer to chapter 8 of the CoreSight TRM for TPIU programmer model. You will go to the offset address at 0x FB0 of the TPIU module and write 0xC5ACCE55 to unlock the module. The TPIU is memory mapped at 0xFFA0_3000.

infocenter.arm.com/.../DDI0314H_coresight_components_trm.pdf

Hi Charles,

I've been trying to get the ETM to work but no success yet. Here's how I initialize it:

Unlocking seems succesful since the lock status register reads back as 0x01 (lock status bit is low).

Here are the J-Jet Trace messages:

At the beginning it says it detects a trace clock, after that it  the data output seems to be all zero and at the end there is a warning which indicates that there is no trace clock. Can anyone confirm if the pinning (shown initial post) is correct?

Regards,

Juergen 

Jürgen,

I can't see the pictures you had added.

• Can you try this with our TMDX570LC43HDK board just to be sure that the hardware is ok?
• Can you please compare your schematic and connector layout with what is suggested in SPRU655?
• I'm also not a trace expert, but shouldn't that setup for the ETM be handled by the IAR IDE?

A few more thoughts:

• Some of the ETM pins are multiplex, however default function is the ETM.
• ETM on this device might require to setup the CTI module.

Best Regards,
Christian

Jürgen,

I did a searched for the trace header you referenced to, the MIPI-20, I guess that is the same as the ARM CoreSight-20.

If that's the case, than I doubt that it will work the CoreSight-20 is meant for SWD and TPIU continuous mode trace only, which I think both aren't supported by Cortex-R4/R5 or at least not by Hercules MCU's, they do only support ETM trace and don't have on chip buffers (ETB). I guess the Mictor 38 would be the right choice for this, didn't found any specification on the IAR web page.

The Mictor 38 brings out way more trace signals then the CoreSight-20. And seems to match what we bring out on TMS570LC4357 in terms of ETM signals:

Mictor 38		Hercules
Pin	ETMv3/TPIU	Ball	Signal
1	NC
2	NC
3	NC
4	NC
5	GND
6	TRACECLK	R10	ETMTRACECLKOUT
7	DBGRQ
8	DBGACK
9	nSRST
10	EXTTRIG
11	TDO	C18	TDO
12	VTREF
13	RTCK	A16	RTCK
14	VSUPPLY
15	TCK	B18	TCK
16	TRACEDATA[7]	E14	ETMDATA[7]
17	TMS	C19	TMS
18	TRACEDATA[6]	E15	ETMDATA[6]
19	TDI	A17	TDI
20	TRACEDATA[5]	F15	ETMDATA[5]
21	nTRST	D18	nTRST
22	TRACEDATA[4]	G15	ETMDATA[4]
23	TRACEDATA[15]	E10	ETMDATA[15]
24	TRACEDATA[3]	H15	ETMDATA[3]
25	TRACEDATA[14]	E11	ETMDATA[14]
26	TRACEDATA[2]	J15	ETMDATA[2]
27	TRACEDATA[13]	E12	ETMDATA[13]
28	TRACEDATA[1]	R13	ETMDATA[1]
29	TRACEDATA[12]	E13	ETMDATA[12]
30	Logic 0
31	TRACEDATA[11]	E6	ETMDATA[11]
32	Logic 0
33	TRACEDATA[10]	E7	ETMDATA[10]
34	Logic 1
35	TRACEDATA[9]	E8	ETMDATA[9]
36	TRACECTL	R11	ETMTRACECTL
37	TRACEDATA[8]	E9	ETMDATA[8]
38	TRACEDATA[0]	R12	ETMDATA[0]

Please note, that you don't need to use all the ETMDATA signals, the ETM interface can be configured to work will less data pins.

Best Regards,
Christian

Hi Christian,

thanks for your help, all these connectors and debug modes are highly confusing. It seems difficult to find out what Hercules and IAR suport and which connections need to be made on which connector. I guess I'll ask IAR if Mictor 38 does it. At the end I want to find a way of tracing with minimum pin count.

Regards,
Juergen

Juergen,

Please consider that the bandwidth will be lower as less data pins you are using. I would suggest to use at least all 8 non multiplexed data pins.
Just realized that the color code I added in the table got lost, so ETMDATA[8..15] are multiplexed and could be spared, but I recommend to keep 0..7.
It would certainly be good to double check with IAR what they require and support with which trace pod.

Best Regards,
Christian

Hi,

it's been a while, IAR had to update their IDE to fully support the trace module. I am experimenting with two HDK-Boards (TMS570LC4357 and TMS570LS3137). I have several different projects to test with, I'll attach (not sure how to do that, seem like I can only insert :))  the two most simple ones for reference. It turns out that tracing always works on the R4 board and never on the R5 board. Christian, the Mictor-38 connector was a good advice, it works. I use an adapter from MIPI-60 to Mictor-38 which still allows 16-Bit wide tracing. When I say work, I mean that the trace windows actually fill with meaningful data. For the R5 board the trace module still detects the trace clock as expected and it can acquire access to the ETM (which is version 3 for both controllers) to turn it on. However, no data actually seems to transfer on the R5. In Halcogen I switched all relevant Pins in multiplexing to the ETM function. That should  not be necessary, it's the default function anyway.

All this tells me that the IAR tools work just fine. To me it seems like the difference is in the two controllers. The R5-HDK is equipped with a TMP version. Could that be the problem?

Regards,
Juergen

5353.TexasInstruments.zip

With the R5, the silicon has an extra thing where you pick between tracing CORE0 or CORE1 even though you can only really use CORE0.
If you don't configure this you get nothing out of the trace port.

I think Charles Tsai has a post somewhere on how to configure this.

Dug up an email from Charles where he explained this to me.

Look at this document: infocenter.arm.com/.../DDI0314H_coresight_components_trm.pdf

Which is the same one he linked to in an earlier post.

There is a register CSTF that you need to program. I think it defaults to 0 but you need to set bit [0] 'Enable Slave Port 0' to enable trace coming out of CPU0 to go through to the ETM.

Hi Anthony,

thanks for your input. Seems like it's not possible to simply set the bit in that register. But I think this should be done by the trace module anyway.

Best Regards,
Juergen

Hi Juergen,

I agree the IAR SW should set the right registers to get the Trace working.
However, for most (all?) Cresight modules it is necessary to unlock the access first. There is a Lock Access register at offset 0xFB0, I believe you need to write 0xC5ACCE55 to this register to get (write) access.

Best Regards,
Christian