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TM4C1294NCPT SSI and UART DMA_RX complete interrupt called endless

My problem is with the SSI and UART interrupt handler, which is called after the few Bytes from the DMA channel. I cannot clear the interrupt flag correctly, therefore the ISR is called in an endless loop. So i also tested it, if it cleared the interrupt flag, but i verified that it is not being cleared.



Code snipped to clear DMA RX interrupt

//*****************************************************************************
//
// The control table used by the uDMA controller.  This table must be aligned
// to a 1024 byte boundary.
//
//*****************************************************************************
#if defined(ewarm)
#pragma data_alignment=1024
uint8_t uDMAControlTable[1024];
#elif defined(ccs)
#pragma DATA_ALIGN(uDMAControlTable, 1024)
uint8_t uDMAControlTable[1024];
#else
uint8_t uDMAControlTable[1024] __attribute__ ((aligned(1024)));
#endif

void  DMAEnable(){
  //
  // Enable the uDMA controller at the system level.  Enable it to continue
  // to run while the processor is in sleep.
  //
  MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
  MAP_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA);

  //
  // Enable the uDMA controller error interrupt.  This interrupt will occur
  // if there is a bus error during a transfer.
  //
  MAP_IntEnable(INT_UDMAERR);

  //
  // Enable the uDMA controller.
  //
  MAP_uDMAEnable();

  //
  // Point at the control table to use for channel control structures.
  //
  MAP_uDMAControlBaseSet(uDMAControlTable);
}

Code snipped to clear DMA RX interrupt


do {
MAP_UARTCharGetNonBlocking(usart->ui32UartnBase);
MAP_UARTIntClear(usart->ui32UartnBase, UART_INT_DMARX); }
while ( (MAP_UARTIntStatus(usart->ui32UartnBase, false) & UART_INT_DMARX) != 0);

  • The UART interrupts are always cleared by wrting 1 to the the UART INT clear register. When the CPU enters the ISR, the corresponding interrupt bi should be cleared. Are there any other interrupts are enabled (errors)?

    Regards,
    QJ