Current HALCOGEN code / RM57 Technical documents do not specify turning on ARM Flash and RAM ECC described in Section 4.3.17 of Cortex-R5 Technical Reference:
Described as B0TCMPCEN and B1TCMPCEN by ARM for RAM and ATCMPCEN for FLASH
Sample functions from other Chips:
_coreEnableRamEcc_:
stmfd sp!, {r0}
mrc p15, #0x00, r0, c1, c0, #0x01
orr r0, r0, #0x0C000000 @Enable RAM ECC in accordance with Section 4.3.17 of Cortex-R5 Technical Reference
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
bx lr
.type _coreEnableRamEcc_, $function
.size _coreEnableRamEcc_,.-_coreEnableRamEcc_
@ Enable Flash ECC
.globl _coreEnableFlashEcc_
_coreEnableFlashEcc_:
stmfd sp!, {r0}
mrc p15, #0x00, r0, c1, c0, #0x01
orr r0, r0, #0x02000000 @Enable Flash ECC in accordance with Section 4.3.17 of Cortex-R5 Technical Reference
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
bx lr
.type _coreEnableFlashEcc_, $function
.size _coreEnableFlashEcc_,.-_coreEnableFlashEcc_
Do these need to be enabled in the RM57 for safe operations?
