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Tiva TM4C I2C Error Results

Bernt Roelofs
Prodigy 80 points
Other Parts Discussed in Thread: TM4C1294KCPDT

We're using a Tiva tm4c1294kcpdt, after upgrading our Stellaris lm3s9d96 project.

We noticed that on the Tiva I2C NACK errors (both Data and Address) weren't being detected, and traced it down to the error status bits not coming through from the Master Control/Status register (I2C_O_MCS in SW, I2CMCS in HW)..

Errata I2C#05 in spmz850e.pdf talks about losing those bits if the read happens in the same system clock period (ie the same 8 nSec in our case, quite a small chance), but we're seeing it consistently.

A post by a TI engineer (e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/343532/1200463#1200463) seems to indicate that a read of the MCS register clears the status bits, and that's what we're seeing as well. No mention of this clearing is made in the datasheet.

I'm posting this question because we'd like a TI engineer to confirm that this is the expected behaviour with the Tiva series, and possibly add to the Tiva Errata.

Obviously it's quite a fundamental change from the Stellaris behaviour, and renders the Peripheral Driver Library I2CMasterErr() function useless.

Thank you, Bernt Roelofs

  • 0
    TI__Guru**** 244400 points
    Hello Bernt,

    This was not an expected behavior where a read of the status bit shall clear the error bits as well. This in essence the Errata I2C#05, since it is a discrepancy when compared to the data sheet.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Prodigy 80 points

    Hi Amit,

    Thank you for your reply. Imho, the behaviour we're seeing is quite different from Errata I2C#05. So are you confirming that any read of the status register clears the reported bits?

    Regards, Bernt

  • 0 in reply to Bernt Roelofs
    TI__Guru**** 244400 points
    Hello Brent,

    Yes, A read of the MCS register shall clear the status bit. The software workaround is to read the MCS register into a variable, check the busy and error status bit in the variable, set another error variable, and when the loop break use the error variable for status of the transaction.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Prodigy 80 points

    Thank you Amit,

    I'm glad you confirmed what we've been seeing, and we implemented a similar solution to what you're describing.

    A (slight) added complication is that you still need to do this in an interrupt service routine, since according to Erratum I2C#5 the status could get lost altogether if the I2CMCS read happens at the wrong time. And that means you can't distinguish between Address and Data NACKs since the interrupt status only records a NACK.

    I guess if you really wanted to you could still read I2CMCS in the ISR, and even if the exact cause of the NACK got lost at least you still know there was an error by checking I2CMRIS. 

    I do hope TI will bring out an additional Erratum. This is such a fundamental issue and cost us a fair bit of time because I basically couldn't believe what I was seeing. TI can help prevent other customers wasting their time.

    Regards, Bernt Roelofs

  • 0 in reply to Bernt Roelofs
    TI__Guru**** 244400 points
    Hello Bernt

    Yes, that is correct. However if the Interrupt Handler is being used, then I do not see why the MCS needs to be read any other part of the code?

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Prodigy 80 points

    Hi Amit,

    I was only suggesting reading the MCS register in the Interrupt Handler (not anywhere else) to be able to distinguish between Data and Address NACKs.


    Regards, Bernt