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Hercules CPU Lockstep compare

Mike Ashman
Intellectual 430 points
Other Parts Discussed in Thread: HALCOGEN

Using the TMS570LS04X. The TRM states that when a CPU lockstep compare failure occurs the register CCM-R4 -compare  is written.

It seems that this behavior is always enabled. What happens when this register is written? Does a chip reset occur? Or should I be reading this register periodically? I.e. How do I know when I have a CPU compare error?

  • 0
    TI__Guru**** 191886 points

    Hi Mike,

      Which specific register are you referring to?

      When there is a CPU lockstep compare failure, the CPSE bit of the CCMSR register will be set to 1. In addition, an error signal is routed to the ESM module. Eventually this will lead to an NMI interrupt to the CPU and at the same time assert the nERROR pin on the device to notify the outside world. Your external ASIC can decide if you want to reset the MCU depending on your application and safety case requirement. 

      The Lockstep compare is always ON. 

  • 0 in reply to Charles Tsai
    Intellectual 430 points
    HI Charles,
    I was referring to the CCMSR register. Really I wanted to verify that I will get an interrupt at the CPU. How do I know where this interrupt is received? I'm using Halcogen and in the generated esm.c file I see the interrupt handler 'esmHighInterrupt'. Is there where I would get an interrupt if a CPU Lockstep error occurred?
  • 0 in reply to Mike Ashman
    TI__Guru**** 191886 points
    Hi Mike,
    If you go to the LS04x datasheet table 6-26 you will find that the CCM-R4 compare error is mapped to Group 2 channel 2. When the CPU lockstep compare failure occurs, the Group 2 Channel 2 bit in the ESMSR2 register in the ESM module will set. The ESM module will then generate an interrupt request to the VIM module. Finally the VIM module will generate a FIQ interrupt request to the CPU.

    In esmHighInterrupt handler you will find out what leads to the ESM error and handle it per your application.