Hi All,
I am sorry for throwing this post about display PWM signal on Logic Analyzer in Keil again.
I did some search but it seems the problem has not solved yet. I generated PWM signals on TM4C123
(following Dr. Valvano's course ) and I could observe the PWM signal in a real oscilloscope. However,
when I tried to display PWM on Logic Analyzer in Keil, there were some errors about writing to/reading from
registers and these seemed weird. For example, the orginal code for activating PWM0 is:
SYSCTL_RCGCPWM_R |= 0x01; // 1) activate PWM0-orginal
and this was error when I used step in (F11) to debug.
If the above code is replaced by
SYSCTL_RCGC0_R |= 0x00100000; // 1) activate PWM0
then there is no error any more.
These two lines of code should be the same but I did not understand why it caused error. I also checked
the address and everything seems correct.
After fixing this problem, any actions to PWM0 is an error
PWM0_0_CTL_R &= 0x00000000; // 4) re-loading down-counting mode
PWM0_0_GENA_R = 0xC8; // low on LOAD, high on CMPA down
// PB6 goes low on LOAD
// PB6 goes high on CMPA down
PWM0_0_LOAD_R = period - 1; // 5) cycles needed to count down to 0
PWM0_0_CMPA_R = duty - 1; // 6) count value when output rises
PWM0_0_CTL_R |= 0x00000001; // 7) start PWM0
PWM0_ENABLE_R |= 0x00000001; // enable PB6/M0PWM0
Can anyone share some experience on this issue? I attach all my project files (zipped in a .zip file)for detail.
Any recommendations are appreciated.
Thanks,
Tuan
void PWM0A_Init(uint16_t period, uint16_t duty){
SYSCTL_RCGC0_R |= 0x00100000; // 1) activate PWM0
// SYSCTL_RCGCPWM_R |= 0x01; // 1) activate PWM0-orginal
SYSCTL_RCGCGPIO_R |= 0x02; // 2) activate port B
while((SYSCTL_PRGPIO_R&0x02) == 0){};
GPIO_PORTB_AFSEL_R |= 0x40; // enable alt funct on PB6
GPIO_PORTB_PCTL_R &= ~0x0F000000; // configure PB6 as PWM0
GPIO_PORTB_PCTL_R |= 0x04000000;
GPIO_PORTB_AMSEL_R &= ~0x40; // disable analog functionality on PB6
GPIO_PORTB_DEN_R |= 0x40; // enable digital I/O on PB6
SYSCTL_RCC_R = 0x00100000 | // 3) use PWM divider
(SYSCTL_RCC_R & (~0x000E0000)); // configure for /2 divider
PWM0_0_CTL_R &= 0x00000000; // 4) re-loading down-counting mode
PWM0_0_GENA_R = 0xC8; // low on LOAD, high on CMPA down
// PB6 goes low on LOAD
// PB6 goes high on CMPA down
PWM0_0_LOAD_R = period - 1; // 5) cycles needed to count down to 0
PWM0_0_CMPA_R = duty - 1; // 6) count value when output rises
PWM0_0_CTL_R |= 0x00000001; // 7) start PWM0
PWM0_ENABLE_R |= 0x00000001; // enable PB6/M0PWM0
}
