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program SSI bit rate in slave mode

Massimiliano Cialdi
Expert 1995 points
Other Parts Discussed in Thread: TM4C1231H6PGE

I have TM4C1231H6PGE, and I have to program SSI in slave mode.

Reading reference manual:

My SysClk is 24576000Hz. Since SSInClk must be 12 times slower than SysClk, it can be at most 2048000Hz, is that right?

So I initialize it with:

    SSIConfigSetExpClk(SSI0_BASE, 24576000UL, SSI_FRF_MOTO_MODE_1, SSI_MODE_SLAVE, 24576000UL/12, 8);

With this setup I have CPSDVSR set to 2 and SCR set to 5, and the I have exacly 12 times slower clock.

I wonder if master *must* send data exacly @2.048MHz or can send at slower bitrate?

best regards

Max

  • 0
    TI__Guru**** 198766 points

    Hi Max,

    For Tm4C123 device, the peripheral clock is the same as the system clock. For master SSI mode, the peripheral clock should be >= 2* bit rate; and for slave mode, the peripheral clock has to be >=12*bit rate.

    In your case, you configure the the bit rate as 2.048MHz. SSI is synchronous interface, and the data is sampled on the trailing edge (or leading edge based on the phase). The actually the bit rate is 2.048MHz.

    Regards,

    QJ

  • 0 in reply to QJ Wang
    Expert 1995 points

    QJ Wang said:
    In your case, you configure the the bit rate as 2.048MHz. SSI is synchronous interface, and the data is sampled on the trailing edge (or leading edge based on the phase). The actually the bit rate is 2.048MHz.

    In my thought this was true for master mode. But in slave mode clock is not generated.

    In my case what happen if I program the SSI as depicted in previous post, but master set its clock to 1.5MHz or 750KHz?

    best regards

    Max

  • 0 in reply to Massimiliano Cialdi
    TI__Guru**** 244440 points
    Hello Max

    There can be only master or slave mode. Both simultaneously is not a valid configuration of the SSI core

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Expert 1995 points

    Amit Ashara said:

    There can be only master or slave mode. Both simultaneously is not a valid configuration of the SSI core

    hallo Amit,

    I restart from the beginning:

    my Tiva has SPI programmed as slave. The SPI clock signal is driven by master, and the master choose the SPI clock speed. In my application the master is a pluggable device so firmware cannot known the SPI clock speed in advice. I only know that it can range from 1.5MHz to about 400KHz.

    So the question is:

    what happen if I program the SSI as slave with but rate set to 2048KHz, but master set its clock to 1.5MHz or 750KHz?

    Or, in other words, what is the meaning of bitrate parameter when SSI is slave?

    best regards

    Max

  • 0 in reply to Massimiliano Cialdi
    TI__Guru**** 244440 points
    Hello Max,

    As long as the master does not cross the limit of SSI slave operational frequency of system_clock/12, there is no issue. The Bit rate parameter is required for the state machine of the slave.

    Regards
    Amit